Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

On 7/11/19 9:57 PM, Nicholas Piggin wrote: > Claudio Carvalho's on June 29, 2019 6:08 am: >> From: Sukadev Bhattiprolu >> >> The ultravisor processor mode is introduced in POWER platforms that >> supports the Protected Execution Facility (PEF). Ultravisor is higher >> privileged than hypervisor

Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

Nicholas Piggin writes: > Claudio Carvalho's on June 29, 2019 6:08 am: >> From: Sukadev Bhattiprolu >> >> The ultravisor processor mode is introduced in POWER platforms that >> supports the Protected Execution Facility (PEF). Ultravisor is higher >> privileged than hypervisor mode. >> >> In PE

Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

Michael Ellerman's on July 11, 2019 10:57 pm: > Claudio Carvalho writes: >> From: Sukadev Bhattiprolu >> >> The ultravisor processor mode is introduced in POWER platforms that >> supports the Protected Execution Facility (PEF). Ultravisor is higher >> privileged than hypervisor mode. >> >> In PEF

Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

Claudio Carvalho's on June 29, 2019 6:08 am: > From: Sukadev Bhattiprolu > > The ultravisor processor mode is introduced in POWER platforms that > supports the Protected Execution Facility (PEF). Ultravisor is higher > privileged than hypervisor mode. > > In PEF enabled platforms, the MSR_S bit

Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

Claudio Carvalho writes: > From: Sukadev Bhattiprolu > > The ultravisor processor mode is introduced in POWER platforms that > supports the Protected Execution Facility (PEF). Ultravisor is higher > privileged than hypervisor mode. > > In PEF enabled platforms, the MSR_S bit is used to indicate i

Re: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

On 2019-06-28 15:08, Claudio Carvalho wrote: From: Sukadev Bhattiprolu The ultravisor processor mode is introduced in POWER platforms that supports the Protected Execution Facility (PEF). Ultravisor is higher privileged than hypervisor mode. In PEF enabled platforms, the MSR_S bit is used to i

[PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit

From: Sukadev Bhattiprolu The ultravisor processor mode is introduced in POWER platforms that supports the Protected Execution Facility (PEF). Ultravisor is higher privileged than hypervisor mode. In PEF enabled platforms, the MSR_S bit is used to indicate if the thread is in secure state. With