On 05/24/2016 02:17 PM, Madhavan Srinivasan wrote:
>
>
> On Monday 23 May 2016 08:48 PM, Shreyas B. Prabhu wrote:
>> POWER ISA v3 defines a new idle processor core mechanism. In summary,
>> a) new instruction named stop is added. This instruction replaces
>> instructions like nap, sleep,
On 05/24/2016 03:54 PM, Gautham R Shenoy wrote:
> Hi Shreyas,
>
> On Mon, May 23, 2016 at 08:48:40PM +0530, Shreyas B. Prabhu wrote:
>> @@ -412,7 +517,8 @@ subcore_state_restored:
>> first_thread_in_core:
>>
>> /*
>> - * First thread in the core waking up from fastsleep. It needs to
>>
Hi Shreyas,
On Mon, May 23, 2016 at 08:48:40PM +0530, Shreyas B. Prabhu wrote:
> @@ -412,7 +517,8 @@ subcore_state_restored:
> first_thread_in_core:
>
> /*
> - * First thread in the core waking up from fastsleep. It needs to
> + * First thread in the core waking up from any state
On Monday 23 May 2016 08:48 PM, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
> a) new instruction named stop is added. This instruction replaces
> instructions like nap, sleep, rvwinkle.
> b) new per thread SPR named PSSCR is added which
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
PSSCR has fo