On Thursday, 8 March 2018 7:22:52 PM AEDT Michael Ellerman wrote:
> Alistair Popple writes:
>
> > Michael,
> >
> > This won't apply cleanly on top of Balbir's MMIO ATSD Flushing patch
> > (https://patchwork.ozlabs.org/patch/848343/). I will resend a v4 which
> > applies
> > cleanly on top of tha
Alistair Popple writes:
> Michael,
>
> This won't apply cleanly on top of Balbir's MMIO ATSD Flushing patch
> (https://patchwork.ozlabs.org/patch/848343/). I will resend a v4 which applies
> cleanly on top of that as the rebase/merge is non-trivial.
I have this (v3) merged in my testing branch (
Michael,
This won't apply cleanly on top of Balbir's MMIO ATSD Flushing patch
(https://patchwork.ozlabs.org/patch/848343/). I will resend a v4 which applies
cleanly on top of that as the rebase/merge is non-trivial.
- Alistair
On Friday, 2 March 2018 4:18:45 PM AEDT Alistair Popple wrote:
> When
When sending TLB invalidates to the NPU we need to send extra flushes due
to a hardware issue. The original implementation would lock the all the
ATSD MMIO registers sequentially before unlocking and relocking each of
them sequentially to do the extra flush.
This introduced a deadlock as it is pos
