On Fri, 2009-03-20 at 06:47 -0500, Kumar Gala wrote:
> On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
>
> > On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
> >> CoreInt provides a mechansim to deliver the IRQ vector directly
> >> into the core on an interrupt (via the SPR EPR) ra
On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to provide
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
> CoreInt provides a mechansim to deliver the IRQ vector directly
> into the core on an interrupt (via the SPR EPR) rather than having
> to go IACK on the PIC. This is suppose to provide an improvment
> in interrupt latency by reducing the time
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to provide an improvment
in interrupt latency by reducing the time to get the IRQ vector.
Signed-off-by: Kumar Gala
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* Fixe
