On Wed, 2011-06-29 at 14:40 -0500, Scott Wood wrote:
> What is the "weird page table format" referred to by the normal miss
> handler?
Not sure :-) Probably the fact that we allocate 64K for PTE pages but
only use 32K of them ?
Cheers,
Ben.
___
Linuxpp
On Wed, 29 Jun 2011 17:50:28 +1000
Benjamin Herrenschmidt wrote:
> On Wed, 2011-06-22 at 16:25 -0500, Scott Wood wrote:
> > On MMUs such as FSL where we can guarantee the entire linear mapping is
> > bolted, we don't need to worry about linear TLB misses. If on top of
> > that we do a full table
On Wed, 2011-06-22 at 16:25 -0500, Scott Wood wrote:
> On MMUs such as FSL where we can guarantee the entire linear mapping is
> bolted, we don't need to worry about linear TLB misses. If on top of
> that we do a full table walk, we get rid of all recursive TLB faults, and
> can dispense with some
On MMUs such as FSL where we can guarantee the entire linear mapping is
bolted, we don't need to worry about linear TLB misses. If on top of
that we do a full table walk, we get rid of all recursive TLB faults, and
can dispense with some state saving. This gains a few percent on
TLB-miss-heavy wo
