On Tue, 2014-08-26 at 16:34 -0500, Aaron Sierra wrote:
> > > +static inline u32 fsl_ifc_version(struct fsl_ifc_regs *regs) {
> > > + return ioread32be(®s->ifc_rev) & FSL_IFC_VERSION_MASK;
> > > +}
> > > +
> > > +static inline int fsl_ifc_bank_count(struct fsl_ifc_regs *regs) {
> > > + return (fsl_i
- Original Message -
> From: "Scott Wood"
> Sent: Tuesday, August 26, 2014 3:48:51 PM
>
> On Tue, 2014-08-26 at 12:31 -0500, Aaron Sierra wrote:
> > Freescale's QorIQ T Series processors support 8 IFC chip selects
> > within a memory map backward compatible with previous P Series
> > proc
On Tue, 2014-08-26 at 12:31 -0500, Aaron Sierra wrote:
> Freescale's QorIQ T Series processors support 8 IFC chip selects
> within a memory map backward compatible with previous P Series
> processors which supported only 4 chip selects.
>
> Signed-off-by: Aaron Sierra
> ---
> drivers/memory/fsl_
Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.
Signed-off-by: Aaron Sierra
---
drivers/memory/fsl_ifc.c| 2 +-
drivers/mtd/nand/fsl_ifc_nand.c | 17 ++
