On Mon, Apr 8, 2019 at 2:39 AM Aneesh Kumar K.V
wrote:
>
>
> Hi Dan,
>
> Dan Williams writes:
>
> > On Wed, Mar 13, 2019 at 2:58 AM Jan Kara wrote:
> >>
> >> On Wed 13-03-19 10:17:17, Aneesh Kumar K.V wrote:
> >> >
> >> > Hi Dan/Andrew/Jan,
> >> >
> >> > "Aneesh Kumar K.V" writes:
> >> >
> >>
Hi Dan,
Dan Williams writes:
> On Wed, Mar 13, 2019 at 2:58 AM Jan Kara wrote:
>>
>> On Wed 13-03-19 10:17:17, Aneesh Kumar K.V wrote:
>> >
>> > Hi Dan/Andrew/Jan,
>> >
>> > "Aneesh Kumar K.V" writes:
>> >
>> > > Architectures like ppc64 use the deposited page table to store hardware
>> > >
On Wed, Mar 13, 2019 at 2:58 AM Jan Kara wrote:
>
> On Wed 13-03-19 10:17:17, Aneesh Kumar K.V wrote:
> >
> > Hi Dan/Andrew/Jan,
> >
> > "Aneesh Kumar K.V" writes:
> >
> > > Architectures like ppc64 use the deposited page table to store hardware
> > > page table slot information. Make sure we dep
On Wed 13-03-19 10:17:17, Aneesh Kumar K.V wrote:
>
> Hi Dan/Andrew/Jan,
>
> "Aneesh Kumar K.V" writes:
>
> > Architectures like ppc64 use the deposited page table to store hardware
> > page table slot information. Make sure we deposit a page table when
> > using zero page at the pmd level for
Hi Dan/Andrew/Jan,
"Aneesh Kumar K.V" writes:
> Architectures like ppc64 use the deposited page table to store hardware
> page table slot information. Make sure we deposit a page table when
> using zero page at the pmd level for hash.
>
> Without this we hit
>
> Unable to handle kernel paging
Architectures like ppc64 use the deposited page table to store hardware
page table slot information. Make sure we deposit a page table when
using zero page at the pmd level for hash.
Without this we hit
Unable to handle kernel paging request for data at address 0x
Faulting instruction add
