Hi Sean,
On Thu, Aug 10, 2023 at 03:58:36PM -0400, Sean Anderson wrote:
> I can look into doing this. It will be in my free time, so it will
> likely be a bit before I can update this series.
I was expecting you'd ask some clarification questions about the RCW
override procedure that I've informa
On Thu, Aug 24, 2023 at 06:09:52PM -0400, Sean Anderson wrote:
> On 8/21/23 19:59, Vladimir Oltean wrote:
> > On Mon, Aug 21, 2023 at 07:39:15PM -0400, Sean Anderson wrote:
> >> Well, I think we should take the opportunity to think about the hardware
> >> which exists and how we plan to model it. I
On 8/21/23 19:59, Vladimir Oltean wrote:
> On Mon, Aug 21, 2023 at 07:39:15PM -0400, Sean Anderson wrote:
>> Well, I think we should take the opportunity to think about the hardware
>> which exists and how we plan to model it. IMO grouping lanes into a
>> single phy simplifies both the phy driver a
On 8/22/23 10:55, Ioana Ciornei wrote:
> On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
>> On 8/21/23 14:13, Ioana Ciornei wrote:
>> > On Mon, Aug 21, 2023 at 01:45:44PM -0400, Sean Anderson wrote:
>> >> Well, we have two pieces of information we need
>> >>
>> >> - What values do w
On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
> On 8/21/23 14:13, Ioana Ciornei wrote:
> > On Mon, Aug 21, 2023 at 01:45:44PM -0400, Sean Anderson wrote:
> >> Well, we have two pieces of information we need
> >>
> >> - What values do we need to program in the PCCRs to select a par
On Mon, Aug 21, 2023 at 07:39:15PM -0400, Sean Anderson wrote:
> Well, I think we should take the opportunity to think about the hardware
> which exists and how we plan to model it. IMO grouping lanes into a
> single phy simplifies both the phy driver and the mac driver.
Ok, but ungrouped for back
On 8/21/23 18:48, Vladimir Oltean wrote:
> On Mon, Aug 21, 2023 at 05:06:46PM -0400, Sean Anderson wrote:
>> On 8/21/23 15:58, Vladimir Oltean wrote:
>> > On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
>> >> After further review, it seems the reason 28g can get away without this
>>
On Mon, Aug 21, 2023 at 05:06:46PM -0400, Sean Anderson wrote:
> On 8/21/23 15:58, Vladimir Oltean wrote:
> > On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
> >> After further review, it seems the reason 28g can get away without this
> >> is because there's a one-to-one mapping betw
On 8/21/23 15:58, Vladimir Oltean wrote:
> On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
>> After further review, it seems the reason 28g can get away without this
>> is because there's a one-to-one mapping between protocol controllers and
>> lanes. Unfortunately, that regularity i
On Mon, Aug 21, 2023 at 02:46:53PM -0400, Sean Anderson wrote:
> After further review, it seems the reason 28g can get away without this
> is because there's a one-to-one mapping between protocol controllers and
> lanes. Unfortunately, that regularity is not present for 10g.
>
> --Sean
There are
On 8/21/23 14:13, Ioana Ciornei wrote:
> On Mon, Aug 21, 2023 at 01:45:44PM -0400, Sean Anderson wrote:
>> Well, we have two pieces of information we need
>>
>> - What values do we need to program in the PCCRs to select a particular
>> mode? This includes whether to e.g. set the KX bits.
>> - Im
On Mon, Aug 21, 2023 at 09:13:49PM +0300, Ioana Ciornei wrote:
> > - We can have one compatible for each SoC, and determine the serdes
> > based on the address. I would like to avoid this...
>
> To me this really seems like a straightforward approach.
+1
On Mon, Aug 21, 2023 at 01:45:44PM -0400, Sean Anderson wrote:
> Well, we have two pieces of information we need
>
> - What values do we need to program in the PCCRs to select a particular
> mode? This includes whether to e.g. set the KX bits.
> - Implied by the above, what protocols are support
On 8/21/23 08:49, Vladimir Oltean wrote:
> Hi Sean,
>
> On Fri, Aug 11, 2023 at 07:36:37PM +0300, Vladimir Oltean wrote:
>> Let me explain that approach, because your mention of "swapping out the
>> bootloaders" makes it appear as if you are not visualising what I am
>> proposing.
>>
>> The Lynx
Hi Sean,
On Fri, Aug 11, 2023 at 07:36:37PM +0300, Vladimir Oltean wrote:
> Let me explain that approach, because your mention of "swapping out the
> bootloaders" makes it appear as if you are not visualising what I am
> proposing.
>
> The Lynx SerDes family has 2 PLLs, and more lanes (4 or 8). E
On Fri, Aug 11, 2023 at 11:43:01AM -0400, Sean Anderson wrote:
> >> > > Here is an illustrative example (sorry, I don't have a board with the
> >> > > right refclk on that PLL, to verify all the way):
> >> > >
> >> > > ... snip ...
> >> >
> >> > (which of course complicates the process of buildin
Hi Sean,
On Thu, Aug 10, 2023 at 03:58:36PM -0400, Sean Anderson wrote:
> As explained previously (and noted by yourself below) 1G and 10G RCWs
> have mutally-incompatible clocking requirements. Now that you have
> documented an alternate solution, it is possible to boot up with one RCW
> and swit
On 8/11/23 11:08, Vladimir Oltean wrote:
> Hi Sean,
>
> On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote:
>> > > At first sight you might appear to have a point related to the fact that
>> > > PLL register writes are necessary, and thus this whole shebang is
>> > > necessary.
>> >
Hi Sean,
On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote:
> > > At first sight you might appear to have a point related to the fact that
> > > PLL register writes are necessary, and thus this whole shebang is
> > > necessary.
> > > But this can all be done using PBI commands, with
Hi Vladimir,
On 8/10/23 06:26, Vladimir Oltean wrote:
> Hi Sean,
>
> On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote:
>> The way things are supposed to work (*if* this works at all) is that the
>> reset state machine starts with a supported PLL / refclk configuration
>> that permi
Hi Sean,
On Tue, Jun 13, 2023 at 05:27:54PM +0300, Vladimir Oltean wrote:
> The way things are supposed to work (*if* this works at all) is that the
> reset state machine starts with a supported PLL / refclk configuration
> that permits a certain subset of protocols, and the SERDES protocols can
>
On Mon, Jun 12, 2023 at 04:46:16PM -0400, Sean Anderson wrote:
> On 6/12/23 12:33, Vladimir Oltean wrote:
> > On Mon, Jun 12, 2023 at 10:35:21AM -0400, Sean Anderson wrote:
> >> > And if SERDES protocol switching was not physically possible, would this
> >> > patch set still have value?
>
> More t
On 6/12/23 12:33, Vladimir Oltean wrote:
> On Mon, Jun 12, 2023 at 10:35:21AM -0400, Sean Anderson wrote:
>> > And if SERDES protocol switching was not physically possible, would this
>> > patch set still have value?
More to the point, did you make any progress in this area?
>> Yes. To e.g. set u
On Mon, Jun 12, 2023 at 10:35:21AM -0400, Sean Anderson wrote:
> > And if SERDES protocol switching was not physically possible, would this
> > patch set still have value?
>
> Yes. To e.g. set up SGMII25 or to fix the clocking situation.
Let me analyze the reasons one by one.
The clocking situat
On 6/10/23 18:21, Vladimir Oltean wrote:
> Hello Sean,
>
> On Fri, Jun 09, 2023 at 03:19:22PM -0400, Sean Anderson wrote:
>> On 5/22/23 11:00, Vladimir Oltean wrote:
>> > On Mon, May 22, 2023 at 10:42:04AM -0400, Sean Anderson wrote:
>> >> Have you had a chance to review this driver?
>> >
>> > Pa
Hello Sean,
On Fri, Jun 09, 2023 at 03:19:22PM -0400, Sean Anderson wrote:
> On 5/22/23 11:00, Vladimir Oltean wrote:
> > On Mon, May 22, 2023 at 10:42:04AM -0400, Sean Anderson wrote:
> >> Have you had a chance to review this driver?
> >
> > Partially / too little (and no, I don't have an answer
On 5/22/23 11:00, Vladimir Oltean wrote:
> On Mon, May 22, 2023 at 10:42:04AM -0400, Sean Anderson wrote:
>> Have you had a chance to review this driver?
>
> Partially / too little (and no, I don't have an answer yet). I am
> debugging a SERDES protocol change procedure from XFI to SGMII.
I'd jus
On Mon, May 22, 2023 at 10:42:04AM -0400, Sean Anderson wrote:
> Have you had a chance to review this driver?
Partially / too little (and no, I don't have an answer yet). I am
debugging a SERDES protocol change procedure from XFI to SGMII.
Hi Vladmir,
On 5/1/23 11:03, Sean Anderson wrote:
> On 4/29/23 13:24, Vladimir Oltean wrote:
>> On Wed, Apr 26, 2023 at 10:50:17AM -0400, Sean Anderson wrote:
>>> > I need to catch up with 14 rounds of patches from you and with the
>>> > discussions that took place on each version, and understand
On 4/29/23 13:24, Vladimir Oltean wrote:
> On Wed, Apr 26, 2023 at 10:50:17AM -0400, Sean Anderson wrote:
>> > I need to catch up with 14 rounds of patches from you and with the
>> > discussions that took place on each version, and understand how you
>> > responded to feedback like "don't remove PH
On Wed, Apr 26, 2023 at 10:50:17AM -0400, Sean Anderson wrote:
> > I need to catch up with 14 rounds of patches from you and with the
> > discussions that took place on each version, and understand how you
> > responded to feedback like "don't remove PHY interrupts without finding
> > out why they
On 4/26/23 06:51, Vladimir Oltean wrote:
On Tue, Apr 25, 2023 at 04:22:32PM -0400, Sean Anderson wrote:
The features which do not work (major protocol changes) are disabled :)
If it would cause this series to be immediately merged, I would remove
KX/KR and 2.5G which are the only untested link
On Tue, Apr 25, 2023 at 04:22:32PM -0400, Sean Anderson wrote:
> The features which do not work (major protocol changes) are disabled :)
>
> If it would cause this series to be immediately merged, I would remove
> KX/KR and 2.5G which are the only untested link modes.
>
> That said, PCS support i
On 4/25/23 15:50, Vladimir Oltean wrote:
> Hello,
>
> On Thu, 13 Apr 2023 12:05:52 -0400, Sean Anderson wrote:
>> This series is ready for review by the phy maintainers. I have addressed
>> all known feedback and there are no outstanding issues.
>>
>> Major reconfiguration of baud rate (e.g. 1G->
Hello,
On Thu, 13 Apr 2023 12:05:52 -0400, Sean Anderson wrote:
> This series is ready for review by the phy maintainers. I have addressed
> all known feedback and there are no outstanding issues.
>
> Major reconfiguration of baud rate (e.g. 1G->10G) does not work.
>
> There are several stand-al
This adds support for the Lynx 10G SerDes found on the QorIQ T-series
and Layerscape series. Due to limited time and hardware, only support
for the LS1046ARDB and LS1088ARDB is added in this initial series.
This series is ready for review by the phy maintainers. I have addressed
all known feedback
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