On Tue, 30 Apr 2019 16:14:35 +1000
Alexey Kardashevskiy wrote:
> On 30/04/2019 15:45, Alistair Popple wrote:
> > Alexey,
> >
> > +void pnv_try_isolate_nvidia_v100(struct pci_dev *bridge)
> > +{
> > + u32 mask, val;
> > + void __iomem *bar0_0, *bar0_12, *bar0_a00
On 30/04/2019 15:45, Alistair Popple wrote:
> Alexey,
>
> +void pnv_try_isolate_nvidia_v100(struct pci_dev *bridge)
> +{
> + u32 mask, val;
> + void __iomem *bar0_0, *bar0_12, *bar0_a0;
> + struct pci_dev *pdev;
> + u16 cmd = 0, cmdmask = PCI_COMMAND_MEMORY;
Alexey,
> >>> +void pnv_try_isolate_nvidia_v100(struct pci_dev *bridge)
> >>> +{
> >>> + u32 mask, val;
> >>> + void __iomem *bar0_0, *bar0_12, *bar0_a0;
> >>> + struct pci_dev *pdev;
> >>> + u16 cmd = 0, cmdmask = PCI_COMMAND_MEMORY;
> >>> +
> >>> + if (!bridge->subordinate)
> >>> +
On 12/04/2019 13:48, Alexey Kardashevskiy wrote:
>
>
> On 12/04/2019 02:52, Alex Williamson wrote:
>> On Thu, 11 Apr 2019 16:48:44 +1000
>> Alexey Kardashevskiy wrote:
>>
>>> The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
>>> (on POWER9) NVLinks. In addition to that, GP
On 12/04/2019 02:52, Alex Williamson wrote:
> On Thu, 11 Apr 2019 16:48:44 +1000
> Alexey Kardashevskiy wrote:
>
>> The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
>> (on POWER9) NVLinks. In addition to that, GPUs themselves have direct
>> peer-to-peer NVLinks in groups o
On Thu, 11 Apr 2019 16:48:44 +1000
Alexey Kardashevskiy wrote:
> The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
> (on POWER9) NVLinks. In addition to that, GPUs themselves have direct
> peer-to-peer NVLinks in groups of 2 to 4 GPUs with no buffers/latches
> between GPUs.
>
The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
(on POWER9) NVLinks. In addition to that, GPUs themselves have direct
peer-to-peer NVLinks in groups of 2 to 4 GPUs with no buffers/latches
between GPUs.
Because of these interconnected NVLinks, the POWERNV platform puts such
in
