Re: [PATCH kernel RFC 0/3] powerpc/pseries/iommu: GPU coherent memory pass through

2018-10-15 Thread Alexey Kardashevskiy
Ping? On 17/09/2018 17:05, Alexey Kardashevskiy wrote: > Ping? > > The problem is still there... > > > On 24/08/2018 13:04, Alexey Kardashevskiy wrote: >> >> >> On 09/08/2018 14:41, Alexey Kardashevskiy wrote: >>> >>> >>> On 25/07/2018 19:50, Alexey Kardashevskiy wrote: I am trying to pas

Re: [PATCH kernel RFC 0/3] powerpc/pseries/iommu: GPU coherent memory pass through

2018-09-17 Thread Alexey Kardashevskiy
Ping? The problem is still there... On 24/08/2018 13:04, Alexey Kardashevskiy wrote: > > > On 09/08/2018 14:41, Alexey Kardashevskiy wrote: >> >> >> On 25/07/2018 19:50, Alexey Kardashevskiy wrote: >>> I am trying to pass through a 3D controller: >>> [0302]: NVIDIA Corporation GV100GL [Tesla V

Re: [PATCH kernel RFC 0/3] powerpc/pseries/iommu: GPU coherent memory pass through

2018-08-23 Thread Alexey Kardashevskiy
On 09/08/2018 14:41, Alexey Kardashevskiy wrote: > > > On 25/07/2018 19:50, Alexey Kardashevskiy wrote: >> I am trying to pass through a 3D controller: >> [0302]: NVIDIA Corporation GV100GL [Tesla V100 SXM2] [10de:1db1] (rev a1) >> >> which has a quite unique feature as coherent memory directl

Re: [PATCH kernel RFC 0/3] powerpc/pseries/iommu: GPU coherent memory pass through

2018-08-08 Thread Alexey Kardashevskiy
On 25/07/2018 19:50, Alexey Kardashevskiy wrote: > I am trying to pass through a 3D controller: > [0302]: NVIDIA Corporation GV100GL [Tesla V100 SXM2] [10de:1db1] (rev a1) > > which has a quite unique feature as coherent memory directly accessible > from a POWER9 CPU via an NVLink2 transport. >

[PATCH kernel RFC 0/3] powerpc/pseries/iommu: GPU coherent memory pass through

2018-07-25 Thread Alexey Kardashevskiy
I am trying to pass through a 3D controller: [0302]: NVIDIA Corporation GV100GL [Tesla V100 SXM2] [10de:1db1] (rev a1) which has a quite unique feature as coherent memory directly accessible from a POWER9 CPU via an NVLink2 transport. So in addition to passing a PCI device + accompanying NPU de