e: [PATCH V4] powerpc/85xx: Add machine check handler to
fix
> PCIe erratum on mpc85xx
>
> On 03/29/2013 03:03:51 AM, Jia Hongtao-B38951 wrote:
> > BTW, I'm still not sure how to deal with LD instruction with
update.
>
> You would need to do the update yourself. Or ju
; > Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
> > > Stuart Yoder
> > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
> > fix
> > > PCIe erratum on mpc85xx
> > >
> > > On 03/14/2013 09:47:58 PM, J
38 AM
> > > To: David Laight
> > > Cc: Jia Hongtao-B38951; Wood Scott-B07421;
> > linuxppc-dev@lists.ozlabs.org;
> > > Stuart Yoder
> > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler
to
> > fix
> > > PCIe erratum on mpc85x
ongtao-B38951; Wood Scott-B07421;
> > linuxppc-dev@lists.ozlabs.org;
> > > Stuart Yoder
> > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
> > fix
> > > PCIe erratum on mpc85xx
> > >
> > > On 03/13/2013 04:40:40 AM, Davi
ubject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
fix
> PCIe erratum on mpc85xx
>
> On 03/13/2013 04:40:40 AM, David Laight wrote:
> > > Hmm, seems there's no probe_user_address() -- for userspace we
> > > basically want the same thing minus the KERNE
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, March 14, 2013 12:38 AM
> To: David Laight
> Cc: Jia Hongtao-B38951; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
On 03/13/2013 04:40:40 AM, David Laight wrote:
> Hmm, seems there's no probe_user_address() -- for userspace we
> basically want the same thing minus the KERNEL_DS. See
> arch/powerpc/perf/callchain.c for an example.
Isn't that just copy_from_user() ?
Plus pagefault_disable/enable().
-Scott
> Hmm, seems there's no probe_user_address() -- for userspace we
> basically want the same thing minus the KERNEL_DS. See
> arch/powerpc/perf/callchain.c for an example.
Isn't that just copy_from_user() ?
David
___
Linuxppc-dev mailing list
13 12:38 AM
> > > To: Jia Hongtao-B38951
> > > Cc: David Laight; Wood Scott-B07421;
linuxppc-dev@lists.ozlabs.org;
> > > Stuart Yoder
> > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler
to
> > fix
> > > PCIe
> Is that OK if I use the following code?
...
> if (is_in_pci_mem_space(addr)) {
> if (!user_mode(regs)) {
> ret = probe_kernel_address(regs->nip, inst);
>
> if (!ret) {
> rd = get_rt(inst);
>
; > Cc: David Laight; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
> > > Stuart Yoder
> > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
> > fix
> > > PCIe erratum on mpc85xx
> > >
> > > On 03/0
e: [PATCH V4] powerpc/85xx: Add machine check handler to
fix
> PCIe erratum on mpc85xx
>
> On 03/07/2013 02:06:05 AM, Jia Hongtao-B38951 wrote:
> > Here is the ideas from Scott:
> > "
> > > +if (is_in_pci_mem_space(addr)) {
> > > +i
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, March 08, 2013 12:38 AM
> To: Jia Hongtao-B38951
> Cc: David Laight; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
On 03/07/2013 02:06:05 AM, Jia Hongtao-B38951 wrote:
Here is the ideas from Scott:
"
> + if (is_in_pci_mem_space(addr)) {
> + inst = *(unsigned int *)regs->nip;
Be careful about taking a fault here. A simple TLB miss should be
safe
given that we shouldn't be accessing PCIe in the m
> In my understanding filling the register could warn the executing process
> an error occurred in some cases. But no way to fix the wrong behavior caused
> by the instruction lost. So let's say that filling the register may benefit
> a little.
IIRC the only ppc instructions that should be accessi
> -Original Message-
> From: David Laight [mailto:david.lai...@aculab.com]
> Sent: Wednesday, March 06, 2013 6:24 PM
> To: Jia Hongtao-B38951; Wood Scott-B07421
> Cc: linuxppc-dev@lists.ozlabs.org; Stuart Yoder
> Subject: RE: [PATCH V4] powerpc/85xx: Add machine ch
> > Yes, that's (one reason) why you'd want to fill in a known value. Note
> > the "for now". :-)
> >
> > -Scott
>
> I think there is no overwhelming reason to fill the destination register
> with 0x.
>
> There's a small chance that 0x is treated as regular data rather
> than an
gt; Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Kumar Gala
> > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to
> > fix
> > > PCIe erratum on mpc85xx
> > >
> > > On 03/04/2013 10:16:10 AM, Stuart Yoder wrote:
> > > > O
On 03/05/2013 04:12:30 AM, Jia Hongtao-B38951 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, March 05, 2013 7:46 AM
> To: Stuart Yoder
> Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Kumar Gala
> Subject: Re: [PATCH V4] powerpc/85xx:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, March 05, 2013 7:46 AM
> To: Stuart Yoder
> Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Kumar Gala
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix
> PCIe erratum on
> -Original Message-
> From: David Laight [mailto:david.lai...@aculab.com]
> Sent: Tuesday, March 05, 2013 1:16 AM
> To: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org
> Cc: Wood Scott-B07421
> Subject: RE: [PATCH V4] powerpc/85xx: Add
On 03/04/2013 10:16:10 AM, Stuart Yoder wrote:
On Mon, Mar 4, 2013 at 2:40 AM, Jia Hongtao
wrote:
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruc
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-check exception is generated to the core
> to allow further pr
On Mon, Mar 4, 2013 at 2:40 AM, Jia Hongtao wrote:
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-check exce
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
goes down. when the link goes down, Non-posted transactions issued
via the ATMU requiring completion result in an instruction stall.
At the same time a machine-check exception is generated to the core
to allow further processing b
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