On Thu, 2015-02-19 at 18:56 -0600, Bjorn Helgaas wrote:
> So there are the two windows of CPU address space that are routed to the
> PHB. And the PHB contains one M32 window and sixteen M64 windows. What
> happens if the PHB receives an access to something that was in one of the
> two CPU addres
On Tue, Feb 10, 2015 at 12:02:31PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2015-02-04 at 17:44 -0600, Bjorn Helgaas wrote:
> > >
> > > diff --git a/Documentation/powerpc/pci_iov_resource_on_powernv.txt
> > > b/Documentation/powerpc/pci_iov_resource_on_powernv.txt
> > > new file mode 100644
On Wed, 2015-02-04 at 17:44 -0600, Bjorn Helgaas wrote:
> >
> > diff --git a/Documentation/powerpc/pci_iov_resource_on_powernv.txt
> > b/Documentation/powerpc/pci_iov_resource_on_powernv.txt
> > new file mode 100644
> > index 000..10d4ac2
> > --- /dev/null
> > +++ b/Documentation/powerpc/pci_
On Thu, Jan 15, 2015 at 10:27:56AM +0800, Wei Yang wrote:
> In order to enable SRIOV on PowerNV platform, the PF's IOV BAR needs to be
> adjusted:
> 1. size expaned
> 2. aligned to M64BT size
>
> This patch documents this change on the reason and how.
>
> Signed-off-by: Wei Yang
> ---
>
In order to enable SRIOV on PowerNV platform, the PF's IOV BAR needs to be
adjusted:
1. size expaned
2. aligned to M64BT size
This patch documents this change on the reason and how.
Signed-off-by: Wei Yang
---
.../powerpc/pci_iov_resource_on_powernv.txt| 215 +++
