Re: [PATCH 9/9] powerpc: A new cache geometry aux vectors

2017-01-30 Thread Benjamin Herrenschmidt
On Tue, 2017-01-31 at 07:27 +1100, Michael Ellerman wrote: > Will need some more macro foo. That or make ppc64_caches ppc_caches, and make it common... I'll look into it. Cheers, Ben.

Re: [PATCH 9/9] powerpc: A new cache geometry aux vectors

2017-01-30 Thread Michael Ellerman
Benjamin Herrenschmidt writes: > diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h > index 730c27e..a128836 100644 > --- a/arch/powerpc/include/asm/elf.h > +++ b/arch/powerpc/include/asm/elf.h > @@ -156,6 +163,14 @@ do {

Re: [PATCH 9/9] powerpc: A new cache geometry aux vectors

2017-01-10 Thread Benjamin Herrenschmidt
On Tue, 2017-01-10 at 10:16 -0600, Paul Clarke wrote: > On 01/08/2017 05:31 PM, Benjamin Herrenschmidt wrote: > > This adds AUX vectors for the L1I,D, L2 and L3 cache levels > > providing for each cache level the size of the cache in bytes > > and the geometry (line size and number of ways). > > >

Re: [PATCH 9/9] powerpc: A new cache geometry aux vectors

2017-01-10 Thread Paul Clarke
On 01/08/2017 05:31 PM, Benjamin Herrenschmidt wrote: This adds AUX vectors for the L1I,D, L2 and L3 cache levels providing for each cache level the size of the cache in bytes and the geometry (line size and number of ways). We chose to not use the existing alpha/sh definition which packs all th

[PATCH 9/9] powerpc: A new cache geometry aux vectors

2017-01-08 Thread Benjamin Herrenschmidt
This adds AUX vectors for the L1I,D, L2 and L3 cache levels providing for each cache level the size of the cache in bytes and the geometry (line size and number of ways). We chose to not use the existing alpha/sh definition which packs all the information in a single entry per cache level as it is