Nicholas Piggin writes:
> On Mon, 24 Jul 2017 21:20:07 +1000
> Nicholas Piggin wrote:
>
>> On Mon, 24 Jul 2017 14:28:00 +1000
>> Benjamin Herrenschmidt wrote:
>>
>> > There is no guarantee that the various isync's involved with
>> > the context switch will order the update of the CPU mask with
On Fri, 2017-08-11 at 21:06 +1000, Nicholas Piggin wrote:
> Other than that your series seems good to me if you repost it you
> can add
>
> Reviewed-by: Nicholas Piggin
>
> This one out of the series is the bugfix so it should go to stable
> as well, right?
Yup.
Ben.
On Mon, 24 Jul 2017 21:20:07 +1000
Nicholas Piggin wrote:
> On Mon, 24 Jul 2017 14:28:00 +1000
> Benjamin Herrenschmidt wrote:
>
> > There is no guarantee that the various isync's involved with
> > the context switch will order the update of the CPU mask with
> > the first TLB entry for the new
On Mon, 2017-07-24 at 21:20 +1000, Nicholas Piggin wrote:
> I think this is the right thing to do, but it should be commented.
> Is hwsync the right barrier? (i.e., it will order the page table walk)
This is an open question, I've asked the architects and HW guys and
waiting for an answer.
That s
On Mon, 24 Jul 2017 14:28:00 +1000
Benjamin Herrenschmidt wrote:
> There is no guarantee that the various isync's involved with
> the context switch will order the update of the CPU mask with
> the first TLB entry for the new context being loaded by the HW.
>
> Be safe here and add a memory barr
There is no guarantee that the various isync's involved with
the context switch will order the update of the CPU mask with
the first TLB entry for the new context being loaded by the HW.
Be safe here and add a memory barrier to order any subsequent
load/store which may bring entries into the TLB.
