Nicholas Piggin writes:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt). So all
> the save/restore handling can be avoided completely. In particular NV
> GPRs do not have to be saved, and MSR does not have to be
On Mon, 5 Mar 2018 10:01:01 +1100
Paul Mackerras wrote:
> On Thu, Mar 01, 2018 at 09:57:34PM +1000, Nicholas Piggin wrote:
> > On Thu, 1 Mar 2018 00:04:39 +0530
> > Vaidyanathan Srinivasan wrote:
> >
> > > * Nicholas Piggin [2017-11-18 00:08:07]:
> [snip]
> > > > diff --git a/arch/powerpc/
On Thu, Mar 01, 2018 at 09:57:34PM +1000, Nicholas Piggin wrote:
> On Thu, 1 Mar 2018 00:04:39 +0530
> Vaidyanathan Srinivasan wrote:
>
> > * Nicholas Piggin [2017-11-18 00:08:07]:
[snip]
> > > diff --git a/arch/powerpc/platforms/powernv/idle.c
> > > b/arch/powerpc/platforms/powernv/idle.c
> >
On Thu, 1 Mar 2018 00:04:39 +0530
Vaidyanathan Srinivasan wrote:
> * Nicholas Piggin [2017-11-18 00:08:07]:
>
> > When stop is executed with EC=ESL=0, it appears to execute like a
> > normal instruction (resuming from NIP when woken by interrupt). So all
> > the save/restore handling can be avo
* Nicholas Piggin [2017-11-18 00:08:07]:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt). So all
> the save/restore handling can be avoided completely. In particular NV
> GPRs do not have to be saved, and MSR doe
When stop is executed with EC=ESL=0, it appears to execute like a
normal instruction (resuming from NIP when woken by interrupt). So all
the save/restore handling can be avoided completely. In particular NV
GPRs do not have to be saved, and MSR does not have to be switched
back to kernel MSR.
So m
