This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the control bit on CPU setup and enables that bit
w
Hi Jack,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.6-rc4 next-20160418]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Jack-Miller/powerpc-Complete-FSCR-context-swit
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the control bit on CPU setup and enables that bit
w
Thanks, yeah, that's more readable and more correct. I'll change it in
the next spin.
- Jack
On Tue, Apr 12, 2016 at 12:40 AM, Segher Boessenkool
wrote:
> Hi,
>
> On Mon, Apr 11, 2016 at 01:57:44PM -0500, Jack Miller wrote:
>> __init_FSCR:
>> mfspr r3,SPRN_FSCR
>> + andi. r3,r3,(~
Hi,
On Mon, Apr 11, 2016 at 01:57:44PM -0500, Jack Miller wrote:
> __init_FSCR:
> mfspr r3,SPRN_FSCR
> + andi. r3,r3,(~FSCR_LM)@L
> ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
> mtspr SPRN_FSCR,r3
> blr
This clears the top 48 bits as well. Shouldn't matter curren
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.
This patch disables the control bit on CPU setup and enables that bit
w
