>> +/*
>> + * Host interrupt handlers may have clobbered these guest-readable
>> + * SPRGs, so we need to reload them here with the guest's values.
>> + */
>> +lwz r3, VCPU_VRSAVE(r4)
>> +lwz r5, VCPU_SHARED_SPRG4(r11)
>> +mtspr SPRN_VRSAVE, r3
>> +lwz
From: Scott Wood
Chips such as e500mc that implement category E.HV in Power ISA 2.06
provide hardware virtualization features, including a new MSR mode for
guest state. The guest OS can perform many operations without trapping
into the hypervisor, including transitions to and from guest userspac
