On Wed, Sep 05, 2007 at 03:27:31PM -0700, Dan Malek wrote:
> On Sep 5, 2007, at 1:59 PM, Scott Wood wrote:
>
> >BTW, it seems I misremembered what the conflict was -- it's not with
> >ioremap space, but with the default location of the consistent memory
> >pool (at 0xff10).
>
> Change the con
On Wed, Sep 05, 2007 at 03:42:03PM -0700, Dan Malek wrote:
> On Sep 5, 2007, at 3:23 PM, Scott Wood wrote:
>
> >The IMMRs I've seen from the bootloader are ff00 (Freescale
> >boards)
> >and fa20 (Embedded Planet). AFAICT, the number of fixed TLB
> >entries
> >is fixed at 4 on these ch
On Sep 5, 2007, at 3:23 PM, Scott Wood wrote:
> The IMMRs I've seen from the bootloader are ff00 (Freescale
> boards)
> and fa20 (Embedded Planet). AFAICT, the number of fixed TLB
> entries
> is fixed at 4 on these chips, so using the fourth for flash
> wouldn't take
> away any gen
On Sep 5, 2007, at 1:59 PM, Scott Wood wrote:
> BTW, it seems I misremembered what the conflict was -- it's not with
> ioremap space, but with the default location of the consistent memory
> pool (at 0xff10).
Change the configuration option to move this somewhere
else, outside of the wired m
On Wed, Sep 05, 2007 at 03:08:28PM -0700, Dan Malek wrote:
> All of this worked in 2.4, many changes were part
> of the evolution in 2.6... configurable pinned entries,
> large page sizes, variations, I didn't keep track of
> all of this. I just assumed I'd have to fix it all if I
> ever needed t
On Sep 5, 2007, at 1:53 PM, Scott Wood wrote:
> Where is the code that checks for pinned TLB entries on 8xx when doing
> ioremap?
I don't know. I haven't been the maintainer for the 2.6
changes.
> Why could this not be done with a 512K mapping? How was this
> even tested, given the obvious
On Wed, Sep 05, 2007 at 03:53:01PM -0500, Scott Wood wrote:
> I didn't change it on a whim, I changed it because ioremap() wasn't
> working the way it currently is.
BTW, it seems I misremembered what the conflict was -- it's not with
ioremap space, but with the default location of the consistent m
On Wed, Sep 05, 2007 at 01:36:43PM -0700, Dan Malek wrote:
>
> On Sep 5, 2007, at 12:27 PM, Scott Wood wrote:
>
> >1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting
> >with
> >the default ioremap region.
>
> The original reason to map 8M was so ioremap()
> could use the same w
On Sep 5, 2007, at 12:27 PM, Scott Wood wrote:
> 1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting
> with
> the default ioremap region.
The original reason to map 8M was so ioremap()
could use the same wired TLB rather than allocate
page table entries. It should also cover al
1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with
the default ioremap region.
2. The wrong register was being loaded into SPRN_MD_RPN.
Signed-off-by: Scott Wood <[EMAIL PROTECTED]>
---
arch/powerpc/kernel/head_8xx.S | 10 +-
1 files changed, 5 insertions(+), 5 dele
On Tue, 28 Aug 2007 15:17:16 -0500
Scott Wood wrote:
> 1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting
> with the default ioremap region.
> 2. The wrong register was being loaded into SPRN_MD_RPN.
>
> Signed-off-by: Scott Wood <[EMAIL PROTECTED]>
Acked-by: Vitaly Bordug <[EMAIL
1. Only map 512K of the IMMR, rather than 8M, to avoid conflicting with
the default ioremap region.
2. The wrong register was being loaded into SPRN_MD_RPN.
Signed-off-by: Scott Wood <[EMAIL PROTECTED]>
---
arch/powerpc/kernel/head_8xx.S | 10 +-
1 files changed, 5 insertions(+), 5 dele
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