Benjamin Herrenschmidt wrote:
>
> Don't 970MP have a shared L2 tho ?
The 970MP UM describes 1MB L2 per core, and the device tree on the
quad G5 reflects that... might be interesting to know what it looks
like on IBM JS21 for comparison's sake, but I think we're okay.
_
On Mon, 2008-12-15 at 16:33 -0600, Nathan Lynch wrote:
> Benjamin Herrenschmidt wrote:
> > On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> > > + /* OF on pmac has nodes instead of properties named "l2-cache"
> > > +* beneath CPU nodes.
> > > +*/
> > > + if (!str
Benjamin Herrenschmidt wrote:
> On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> > + /* OF on pmac has nodes instead of properties named "l2-cache"
> > +* beneath CPU nodes.
> > +*/
> > + if (!strcmp(np->type, "cpu"))
> > + for_each_child_of_node(np
Benjamin Herrenschmidt wrote:
> On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> > + /* OF on pmac has nodes instead of properties named "l2-cache"
> > +* beneath CPU nodes.
> > +*/
> > + if (!strcmp(np->type, "cpu"))
> > + for_each_child_of_node(np
On Wed, 2008-12-10 at 18:46 -0600, Nathan Lynch wrote:
> + /* OF on pmac has nodes instead of properties named "l2-cache"
> +* beneath CPU nodes.
> +*/
> + if (!strcmp(np->type, "cpu"))
> + for_each_child_of_node(np, child)
> + if (!st
We have more than one piece of code that looks up cache nodes manually
using the "l2-cache" property. Add a common helper routine which does
this and handles ePAPR's "next-level-cache" property as well as
powermac.
Signed-off-by: Nathan Lynch <[EMAIL PROTECTED]>
---
arch/powerpc/include/asm/prom
