On Monday 24 March 2008, Josh Boyer wrote:
> > diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c
> > b/arch/powerpc/sysdev/ppc4xx_soc.c new file mode 100644
> > index 000..4847555
> > --- /dev/null
> > +++ b/arch/powerpc/sysdev/ppc4xx_soc.c
> > @@ -0,0 +1,178 @@
> > +/*
> > + * IBM/AMCC PPC4xx SoC
On Tue, 25 Mar 2008 07:59:15 +1100
Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote:
>
> On Mon, 2008-03-24 at 08:39 -0500, Josh Boyer wrote:
> > > +
> > > + local_irq_save(flags);
> > > + asm volatile ("sync" ::: "memory");
> >
> > Perhaps just call iosync() for these instead of the ope
On Mon, 2008-03-24 at 08:39 -0500, Josh Boyer wrote:
> > +
> > + local_irq_save(flags);
> > + asm volatile ("sync" ::: "memory");
>
> Perhaps just call iosync() for these instead of the open coded asm
> volatile stuff?
Not sure about that. iosync() will do a sync but it's not meant at be
On Sat, 22 Mar 2008 11:28:56 +0100
Stefan Roese <[EMAIL PROTECTED]> wrote:
> This patch adds support for the 256k L2 cache found on some IBM/AMCC
> 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
> which currently "only" adds the L2 cache init code. Other common 4xx
> stuff ca
This patch adds support for the 256k L2 cache found on some IBM/AMCC
4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
which currently "only" adds the L2 cache init code. Other common 4xx
stuff can be added later here.
The L2 cache handling code is a copy of Eugene's code in arc
