Michael Neuling [mi...@neuling.org] wrote:
| Suka,
|
| One of these two patches breaks pmac32_defconfig and I suspect all other
| 32 bit configs (against mainline)
|
| arch/powerpc/perf/core-book3s.c: In function 'record_and_restart':
| arch/powerpc/perf/core-book3s.c:1632:4: error: passing argum
errors!
Mikey
Sukadev Bhattiprolu wrote:
> From: Sukadev Bhattiprolu
> Date: Wed, 8 May 2013 22:59:29 -0700
> Subject: [PATCH 1/2] perf/Power7: Save dcache_src fields in sample record.
>
> Power7 saves the "perf-event vector" information in the mmcra register.
Stephane Eranian [eran...@google.com] wrote:
| > Further, in the above REM_CCE1 case, Power7 can also identify if the data
came
| > from the L2 or L3 cache of another core on the same chip. To describe this
to
| > user space, we propose to set ->mem_lvl to:
| >
| > PERF_MEM_LVL_REM_CCE1|P
Anshuman Khandual [khand...@linux.vnet.ibm.com] wrote:
| > The former approach seems less confusing and this patch uses that approach.
| >
|
| Yeah, the former approach is simpler and makes sense.
Ok. Seems to make sense at least on Power.
| > + * We use the table, dcache_src_map, to map this
>
> AFAICT, Power7 supports one extra level in the cache-hierarchy, so we propose
> to add a new cache level, REM_CCE3 shown above.
>
> To maintain consistency in terminology (i.e 2-hops = remote, 3-hops =
> distant),
> I propose leaving the REM_MEM1 unused and adding another level, REM_MEM3.
>
From: Sukadev Bhattiprolu
Date: Wed, 8 May 2013 22:59:29 -0700
Subject: [PATCH 1/2] perf/Power7: Save dcache_src fields in sample record.
Power7 saves the "perf-event vector" information in the mmcra register.
Included in this event vector is a "data-cache source" field which
