Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-25 Thread Alexander Graf
On 26.05.15 02:14, Sam Bobroff wrote: > On Mon, May 25, 2015 at 11:08:08PM +0200, Alexander Graf wrote: >> >> >> On 20.05.15 07:26, Sam Bobroff wrote: >>> In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64 >>> bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it i

Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-25 Thread Sam Bobroff
On Mon, May 25, 2015 at 11:08:08PM +0200, Alexander Graf wrote: > > > On 20.05.15 07:26, Sam Bobroff wrote: > > In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64 > > bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is > > accessed as such. > > > > This patch

Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-25 Thread Alexander Graf
On 20.05.15 07:26, Sam Bobroff wrote: > In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64 > bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is > accessed as such. > > This patch corrects places where it is accessed as a 32 bit field by a > 64 bit kernel. I

Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-20 Thread Paul Mackerras
On Wed, May 20, 2015 at 05:35:08PM -0500, Scott Wood wrote: > > It's nominally a 64-bit register, but the upper 32 bits are reserved in > ISA 2.06. Do newer ISAs or certain implementations define things in the > upper 32 bits, or is this just about the asm accesses being wrong on > big-endian? I

Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-20 Thread Scott Wood
On Wed, 2015-05-20 at 15:26 +1000, Sam Bobroff wrote: > In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64 > bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is > accessed as such. > > This patch corrects places where it is accessed as a 32 bit field by a > 64

Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-20 Thread Paul Mackerras
On Wed, May 20, 2015 at 03:26:12PM +1000, Sam Bobroff wrote: > In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64 > bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is > accessed as such. > > This patch corrects places where it is accessed as a 32 bit field by

[PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling

2015-05-19 Thread Sam Bobroff
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64 bit field (e.g. in kvm_regs and kvm_vcpu_arch) and in most places it is accessed as such. This patch corrects places where it is accessed as a 32 bit field by a 64 bit kernel. In some cases this is via a 32 bit load or store inst