On Wed, 4 Mar 2009 20:46:58 +0300
Anton Vorontsov wrote:
> On Sat, Feb 21, 2009 at 04:57:57PM +0100, Pierre Ossman wrote:
> >
> > We can most likely do some micro-optimisation do make the compare part
> > cheaper, but the point was to avoid a function call for all the
> > properly implemented co
On Sat, Feb 21, 2009 at 04:57:57PM +0100, Pierre Ossman wrote:
> On Fri, 13 Feb 2009 17:40:39 +0300
> Anton Vorontsov wrote:
>
> >
> > No, on eSDHC the registers are big-endian, 32-bit width, with, for
> > example, two 16-bit "logical" registers packed into it.
> >
> > That is,
> >
> > 0x4 0
On Fri, 13 Feb 2009 17:40:39 +0300
Anton Vorontsov wrote:
>
> No, on eSDHC the registers are big-endian, 32-bit width, with, for
> example, two 16-bit "logical" registers packed into it.
>
> That is,
>
> 0x4 0x5 0x6 0x7
> |:|
> | BLKCNT : BLKSZ |
> |:|
> 31
On Sun, Feb 08, 2009 at 09:50:20PM +0100, Pierre Ossman wrote:
> On Fri, 6 Feb 2009 21:06:45 +0300
> Anton Vorontsov wrote:
> > Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
> > read{l,b,w}).
> >
> > With this patch drivers may change memory accessors, so that we can
> > s
On Fri, 6 Feb 2009 21:06:45 +0300
Anton Vorontsov wrote:
> Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
> read{l,b,w}).
>
> With this patch drivers may change memory accessors, so that we can
> support hosts with "weird" IO memory access requirments.
>
> For example, in
Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).
With this patch drivers may change memory accessors, so that we can
support hosts with "weird" IO memory access requirments.
For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit
width, with big-endi
