Le 18/03/2025 à 18:29, Shivaprasad G Bhat a écrit :
On POWER systems, when the device is behind the io expander,
not all PCI slots would have the PCI_INTERRUPT_LINE connected.
The firmware assigns a valid PCI_INTERRUPT_PIN though. In such
configuration, the irq_info ioctl currently advertizes
On Thu, 20 Mar 2025 23:24:49 +0530
Shivaprasad G Bhat wrote:
> On 3/18/25 11:28 PM, Alex Williamson wrote:
> > On Tue, 18 Mar 2025 17:29:21 +
> > Shivaprasad G Bhat wrote:
> >
> >> On POWER systems, when the device is behind the io expander,
> >> not all PCI slots would have the PCI_INTERR
On 3/18/25 11:28 PM, Alex Williamson wrote:
On Tue, 18 Mar 2025 17:29:21 +
Shivaprasad G Bhat wrote:
On POWER systems, when the device is behind the io expander,
not all PCI slots would have the PCI_INTERRUPT_LINE connected.
The firmware assigns a valid PCI_INTERRUPT_PIN though. In such
co
On Tue, 18 Mar 2025 17:29:21 +
Shivaprasad G Bhat wrote:
> On POWER systems, when the device is behind the io expander,
> not all PCI slots would have the PCI_INTERRUPT_LINE connected.
> The firmware assigns a valid PCI_INTERRUPT_PIN though. In such
> configuration, the irq_info ioctl current
On POWER systems, when the device is behind the io expander,
not all PCI slots would have the PCI_INTERRUPT_LINE connected.
The firmware assigns a valid PCI_INTERRUPT_PIN though. In such
configuration, the irq_info ioctl currently advertizes the
irq count as 1 as the PCI_INTERRUPT_PIN is valid.
Th
