On Wed, Aug 21, 2013 at 07:28:54AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2013-08-20 at 20:16 +0800, Kevin Hao wrote:
>
> > Dummy question: What does the ifetch buffers mean? The instruction fetch
> > pipeline or instruction dispatch pipeline? Shouldn't all the prefetched
> > instructions
On Tue, 2013-08-20 at 20:16 +0800, Kevin Hao wrote:
> Dummy question: What does the ifetch buffers mean? The instruction fetch
> pipeline or instruction dispatch pipeline? Shouldn't all the prefetched
> instructions in these buffers be discarded by isync?
Architecturally isync doesn't have to tos
On Mon, Aug 19, 2013 at 10:45:35PM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-08-19 at 19:50 +0800, Kevin Hao wrote:
> > On Mon, Aug 19, 2013 at 01:37:17PM +1000, Benjamin Herrenschmidt wrote:
> > > On Mon, 2013-08-19 at 13:36 +1000, Benjamin Herrenschmidt wrote:
> > >
> > > > The semanti
On Mon, 2013-08-19 at 19:50 +0800, Kevin Hao wrote:
> On Mon, Aug 19, 2013 at 01:37:17PM +1000, Benjamin Herrenschmidt wrote:
> > On Mon, 2013-08-19 at 13:36 +1000, Benjamin Herrenschmidt wrote:
> >
> > > The semantic of this function is to make data executable. Even if the
> > > implementation ha
On Mon, Aug 19, 2013 at 01:37:17PM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-08-19 at 13:36 +1000, Benjamin Herrenschmidt wrote:
>
> > The semantic of this function is to make data executable. Even if the
> > implementation has a snooping icache, it *still* needs to make sure
> > prefetc
On Mon, 2013-08-19 at 13:36 +1000, Benjamin Herrenschmidt wrote:
> The semantic of this function is to make data executable. Even if the
> implementation has a snooping icache, it *still* needs to make sure
> prefetched code is tossed out of the pipeline which is what isync
> should provide.
>
>
To: Benjamin Herrenschmidt
> > Cc: linuxppc
> > Subject: [PATCH] powerpc: add the missing required isync for the coherent
> > icache flush
> >
> > Even we don't need to flush the dcache and invalidate the icache
> > on the CPU which has coherent icache.
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+b40534=freescale@lists.ozlabs.org] On Behalf Of Kevin Hao
> Sent: Thursday, August 15, 2013 7:56 PM
> To: Benjamin Herrenschmidt
> Cc: linuxppc
> Subject: [PATCH] powerpc: add the missing r
Even we don't need to flush the dcache and invalidate the icache
on the CPU which has coherent icache. But we do need an isync to
discard the prefetched instructions in this case.
Signed-off-by: Kevin Hao
---
arch/powerpc/kernel/misc_32.S | 2 ++
arch/powerpc/kernel/misc_64.S | 1 +
2 files chan
