On Wed, 2008-06-18 at 15:29 +1000, Paul Mackerras wrote:
> At present, if we have a kernel with a 64kB page size, and some
> process maps something that has to be mapped with 4kB pages (such as a
> cache-inhibited mapping on POWER5+, or the eHCA infiniband queue-pair
> pages), we change the process
At present, if we have a kernel with a 64kB page size, and some
process maps something that has to be mapped with 4kB pages (such as a
cache-inhibited mapping on POWER5+, or the eHCA infiniband queue-pair
pages), we change the process to use 4kB pages everywhere. This hurts
the performance of HPC
