On Mon, 19 Feb 2018, Balbir Singh wrote:
> Good point, although I think the acquire_* function itself may be called
> from a higher layer with the mmap_sem always held. I wonder if we need
> barriers around get and put mmio_atsd_reg.
I agree with the need for memory barriers. FWIW, page tables
> > Shouldn't that be enforced with READ_ONCE() then?
Yep, I can add that.
> Good point, although I think the acquire_* function itself may be called
> from a higher layer with the mmap_sem always held. I wonder if we need
> barriers around get and put mmio_atsd_reg.
test_and_set_bit() should im
On Thu, 15 Feb 2018 19:11:19 -0800
Mark Hairgrove wrote:
> On Wed, 14 Feb 2018, Alistair Popple wrote:
>
> > > > +struct mmio_atsd_reg {
> > > > + struct npu *npu;
> > > > + int reg;
> > > > +};
> > > > +
> > >
> > > Is it just easier to move reg to inside of struct npu?
> >
>
On Wed, 14 Feb 2018, Alistair Popple wrote:
> > > +struct mmio_atsd_reg {
> > > + struct npu *npu;
> > > + int reg;
> > > +};
> > > +
> >
> > Is it just easier to move reg to inside of struct npu?
>
> I don't think so, struct npu is global to all npu contexts where as this is
> specific to the
> > +struct mmio_atsd_reg {
> > + struct npu *npu;
> > + int reg;
> > +};
> > +
>
> Is it just easier to move reg to inside of struct npu?
I don't think so, struct npu is global to all npu contexts where as this is
specific to the given invalidation. We don't have enough registers to assign
e
On Tue, 13 Feb 2018 14:17:34 +1100
Alistair Popple wrote:
> When sending TLB invalidates to the NPU we need to send extra flushes due
> to a hardware issue. The original implementation would lock the all the
> ATSD MMIO registers sequentially before unlocking and relocking each of
> them sequenti
When sending TLB invalidates to the NPU we need to send extra flushes due
to a hardware issue. The original implementation would lock the all the
ATSD MMIO registers sequentially before unlocking and relocking each of
them sequentially to do the extra flush.
This introduced a deadlock as it is pos
