On Apr 28, 2011, at 2:00 AM, Prabhakar Kushwaha wrote:
> Create the dts files for each core and splits the devices between the two
> cores
> for P1020RDB.
>
> Core0 has core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, eth1, eth2,
> sdhc, crypto, global-util, message, pci0, pci1, msi.
>
Create the dts files for each core and splits the devices between the two cores
for P1020RDB.
Core0 has core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, eth1, eth2,
sdhc, crypto, global-util, message, pci0, pci1, msi.
Core1 has l2, eth0, crypto.
MPIC is shared between two cores but each c
