Re: [PATCH] powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

2008-12-05 Thread Nathan Lynch
Benjamin Herrenschmidt wrote: > On Fri, 2008-12-05 at 06:08 -0500, Josh Boyer wrote: > > Shouldn't there also be a next-level-cache property added to the cpu > > node that references this? > > > It would be nice indeed, it would allow the kernel to expose the cache > info in sysfs Currently the k

Re: [PATCH] powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

2008-12-05 Thread Stefan Roese
On Friday 05 December 2008, Benjamin Herrenschmidt wrote: > On Fri, 2008-12-05 at 06:08 -0500, Josh Boyer wrote: > > Shouldn't there also be a next-level-cache property added to the cpu > > node that references this? > > It would be nice indeed, it would allow the kernel to expose the cache > info

Re: [PATCH] powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

2008-12-05 Thread Benjamin Herrenschmidt
On Fri, 2008-12-05 at 06:08 -0500, Josh Boyer wrote: > Shouldn't there also be a next-level-cache property added to the cpu > node that references this? > It would be nice indeed, it would allow the kernel to expose the cache info in sysfs Cheers, Ben. __

Re: [PATCH] powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

2008-12-05 Thread Josh Boyer
On Fri, 5 Dec 2008 07:08:52 +0100 Stefan Roese <[EMAIL PROTECTED]> wrote: > With this patch the L2 cache is enabled on Canyonlands to increase the > overall performance. There is a known cache coherency issue with the L2 > cache, but this is related to the high bandwidth (HB) PLB segment where >

[PATCH] powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file

2008-12-04 Thread Stefan Roese
With this patch the L2 cache is enabled on Canyonlands to increase the overall performance. There is a known cache coherency issue with the L2 cache, but this is related to the high bandwidth (HB) PLB segment where the memory address is 0x8.. (low bandwidth PLB segment is mapped to 0x0.