On Thu, 28 Oct 2021 23:30:43 +1000, Nicholas Piggin wrote:
> A e5500 machine running a 32-bit kernel sometimes hangs at boot,
> seemingly going into an infinite loop of instruction storage interrupts.
> The ESR SPR has a value of 0x80 (store) when this happens, which is
> likely set by a previo
Excerpts from Daniel Axtens's message of October 29, 2021 8:13 am:
> Hi Nick,
>
>> A e5500 machine running a 32-bit kernel sometimes hangs at boot,
>> seemingly going into an infinite loop of instruction storage interrupts.
>> The ESR SPR has a value of 0x80 (store) when this happens, which is
Excerpts from Christophe Leroy's message of October 28, 2021 11:52 pm:
>
>
> Le 28/10/2021 à 15:30, Nicholas Piggin a écrit :
>> A e5500 machine running a 32-bit kernel sometimes hangs at boot,
>> seemingly going into an infinite loop of instruction storage interrupts.
>> The ESR SPR has a value
Hi Nick,
> A e5500 machine running a 32-bit kernel sometimes hangs at boot,
> seemingly going into an infinite loop of instruction storage interrupts.
> The ESR SPR has a value of 0x80 (store) when this happens, which is
> likely set by a previous store. An instruction TLB miss interrupt would
Le 28/10/2021 à 15:30, Nicholas Piggin a écrit :
A e5500 machine running a 32-bit kernel sometimes hangs at boot,
seemingly going into an infinite loop of instruction storage interrupts.
The ESR SPR has a value of 0x80 (store) when this happens, which is
likely set by a previous store. An
A e5500 machine running a 32-bit kernel sometimes hangs at boot,
seemingly going into an infinite loop of instruction storage interrupts.
The ESR SPR has a value of 0x80 (store) when this happens, which is
likely set by a previous store. An instruction TLB miss interrupt would
then leave ESR un
