On Fri, Aug 17, Matt Sealey wrote:
> Setting them to ~0x5 will set them to 0 (legacy mode) and they will always
> read
> back as 0 (legacy mode.. sigh) even if in native mode.
The pci_dev->class needs updating as well, see second version of the
patch.
The built-in IDE controller is configured in legacy mode,
but the PCI registers advertise native mode.
Force the PCI class into legacy mode. This allows pata_via to access
two drives.
The Pegasos specific irq enforcement in the via82cxxx driver
must stay because there is aparently no generic way to
The programming interface register is definitely writable, but the VIA IDE docs
state that certain bits will always read 0 - setting '0x5' in my original patch
set those two bits so it was forced into native mode if it wasn't already.
Setting them to ~0x5 will set them to 0 (legacy mode) and they
On Fri, Aug 17, Olaf Hering wrote:
Still not 100% perfect.
> + prom_printf("Fixing up IDE class-code on Pegasos...\n");
> + rc = prom_getprop(ph, "class-code", prop, sizeof(u32));
> + if (rc == sizeof(u32)) {
> + prop[0] &= ~0x5;
> +
The built-in IDE controller is configured in legacy mode,
but the PCI registers advertise native mode.
Force the PCI class into legacy mode. This allows pata_via to access
two drives.
The Pegasos specific irq enforcement in the via82cxxx driver
can be removed.
Tested on Pegasos2 with firmware ver
