On Jun 2, 2008, at 4:26 PM, Nathan Lynch wrote:
Segher Boessenkool wrote:
The PowerPC binding defines an "l2-cache" property for this (it
points from CPU node to L2 cache node, from L2 cache node to L3
cache node, from L3 cache node to L4 cache node, etc.)
So looking at the PPC binding its
Segher Boessenkool wrote:
>>>
>>> The PowerPC binding defines an "l2-cache" property for this (it
>>> points from CPU node to L2 cache node, from L2 cache node to L3
>>> cache node, from L3 cache node to L4 cache node, etc.)
>>
>> So looking at the PPC binding its not terrible clear about "l3-cache
Added next-level-cache to the L1 and a reference to the new L2 label.
Where is this property defined? I can't find it.
The PowerPC binding defines an "l2-cache" property for this (it
points from CPU node to L2 cache node, from L2 cache node to L3
cache node, from L3 cache node to L4 cache node
On May 30, 2008, at 4:49 PM, Segher Boessenkool wrote:
Added next-level-cache to the L1 and a reference to the new L2 label.
Where is this property defined? I can't find it.
The PowerPC binding defines an "l2-cache" property for this (it
points from CPU node to L2 cache node, from L2 cache
On May 30, 2008, at 4:49 PM, Segher Boessenkool wrote:
Added next-level-cache to the L1 and a reference to the new L2 label.
Where is this property defined? I can't find it.
its in ePAPR.
The PowerPC binding defines an "l2-cache" property for this (it
points from CPU node to L2 cache nod
Added next-level-cache to the L1 and a reference to the new L2 label.
Where is this property defined? I can't find it.
The PowerPC binding defines an "l2-cache" property for this (it
points from CPU node to L2 cache node, from L2 cache node to L3
cache node, from L3 cache node to L4 cache node
Added next-level-cache to the L1 and a reference to the new L2 label.
---
In my powerpc-next branch.
arch/powerpc/boot/dts/ksi8560.dts |3 ++-
arch/powerpc/boot/dts/mpc8540ads.dts |3 ++-
arch/powerpc/boot/dts/mpc8541cds.dts |3 ++-
arch/powerpc/boot/dts/mpc8544ds.dts|
