Re: [1/2] powernv/npu: Do a PID GPU TLB flush when invalidating a large address range

On Tue, 2018-04-17 at 09:11:28 UTC, Alistair Popple wrote: > The NPU has a limited number of address translation shootdown (ATSD) > registers and the GPU has limited bandwidth to process ATSDs. This can > result in contention of ATSD registers leading to soft lockups on some > threads, particularly

Re: [PATCH 1/2] powernv/npu: Do a PID GPU TLB flush when invalidating a large address range

Sorry, forgot to include: Fixes: 1ab66d1fbada ("powerpc/powernv: Introduce address translation services for Nvlink2") Thanks On Tuesday, 17 April 2018 7:11:28 PM AEST Alistair Popple wrote: > The NPU has a limited number of address translation shootdown (ATSD) > registers and the GPU has limite

Re: [PATCH 1/2] powernv/npu: Do a PID GPU TLB flush when invalidating a large address range

On Tue, Apr 17, 2018 at 7:17 PM, Balbir Singh wrote: > On Tue, Apr 17, 2018 at 7:11 PM, Alistair Popple > wrote: >> The NPU has a limited number of address translation shootdown (ATSD) >> registers and the GPU has limited bandwidth to process ATSDs. This can >> result in contention of ATSD regis

Re: [PATCH 1/2] powernv/npu: Do a PID GPU TLB flush when invalidating a large address range

On Tue, Apr 17, 2018 at 7:11 PM, Alistair Popple wrote: > The NPU has a limited number of address translation shootdown (ATSD) > registers and the GPU has limited bandwidth to process ATSDs. This can > result in contention of ATSD registers leading to soft lockups on some > threads, particularly w

[PATCH 1/2] powernv/npu: Do a PID GPU TLB flush when invalidating a large address range

The NPU has a limited number of address translation shootdown (ATSD) registers and the GPU has limited bandwidth to process ATSDs. This can result in contention of ATSD registers leading to soft lockups on some threads, particularly when invalidating a large address range in pnv_npu2_mn_invalidate_