On Mon, Aug 13, 2007 at 04:31:03PM +0400, Valentine Barshak wrote:
[snip]
> >> Ok, here's a patch which fixes up the flow handling on the UIC. It
> >> needs some polish yet, but should be ok to test. Valentine, can you
> >> test this on your setup, *without* your original proposed patch.
> >> Eve
David Gibson wrote:
> On Fri, Aug 03, 2007 at 04:23:46PM +1000, David Gibson wrote:
>> On Fri, Aug 03, 2007 at 02:57:05PM +1000, David Gibson wrote:
>>> On Fri, Aug 03, 2007 at 11:18:09AM +1000, Benjamin Herrenschmidt wrote:
On Thu, 2007-08-02 at 13:48 +1000, David Gibson wrote:
> On Mon,
On Fri, Aug 03, 2007 at 04:23:46PM +1000, David Gibson wrote:
> On Fri, Aug 03, 2007 at 02:57:05PM +1000, David Gibson wrote:
> > On Fri, Aug 03, 2007 at 11:18:09AM +1000, Benjamin Herrenschmidt wrote:
> > > On Thu, 2007-08-02 at 13:48 +1000, David Gibson wrote:
> > > > On Mon, Jul 30, 2007 at 08:3
Josh Boyer wrote:
> On Thu, 2 Aug 2007 13:48:48 +1000
> David Gibson <[EMAIL PROTECTED]> wrote:
>
>> On Mon, Jul 30, 2007 at 08:35:17PM +0400, Valentine Barshak wrote:
>>> PPC44x cascade UIC irq handler fix.
>>>
>>> According to PPC44x UM, if an interrupt is configured as
>>> level-sensitive, and
On Fri, Aug 03, 2007 at 02:57:05PM +1000, David Gibson wrote:
> On Fri, Aug 03, 2007 at 11:18:09AM +1000, Benjamin Herrenschmidt wrote:
> > On Thu, 2007-08-02 at 13:48 +1000, David Gibson wrote:
> > > On Mon, Jul 30, 2007 at 08:35:17PM +0400, Valentine Barshak wrote:
> > > > PPC44x cascade UIC irq
On Fri, Aug 03, 2007 at 11:18:09AM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2007-08-02 at 13:48 +1000, David Gibson wrote:
> > On Mon, Jul 30, 2007 at 08:35:17PM +0400, Valentine Barshak wrote:
> > > PPC44x cascade UIC irq handler fix.
> > >
> > > According to PPC44x UM, if an interrupt is c
On Thu, 2007-08-02 at 13:48 +1000, David Gibson wrote:
> On Mon, Jul 30, 2007 at 08:35:17PM +0400, Valentine Barshak wrote:
> > PPC44x cascade UIC irq handler fix.
> >
> > According to PPC44x UM, if an interrupt is configured as level-sensitive,
> > and a clear is attempted on the UIC_SR, the UIC_
On Thu, 2 Aug 2007 13:48:48 +1000
David Gibson <[EMAIL PROTECTED]> wrote:
> On Mon, Jul 30, 2007 at 08:35:17PM +0400, Valentine Barshak wrote:
> > PPC44x cascade UIC irq handler fix.
> >
> > According to PPC44x UM, if an interrupt is configured as
> > level-sensitive, and a clear is attempted on
On Mon, Jul 30, 2007 at 08:35:17PM +0400, Valentine Barshak wrote:
> PPC44x cascade UIC irq handler fix.
>
> According to PPC44x UM, if an interrupt is configured as level-sensitive,
> and a clear is attempted on the UIC_SR, the UIC_SR field is not
> cleared if the incoming interrupt signal is at
PPC44x cascade UIC irq handler fix.
According to PPC44x UM, if an interrupt is configured as level-sensitive,
and a clear is attempted on the UIC_SR, the UIC_SR field is not
cleared if the incoming interrupt signal is at the asserted polarity.
This causes us to enter a cascade handler twice, since
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