> -Original Message-
> From: Borislav Petkov
> Sent: Donnerstag, 14. März 2024 17:34
> To: Willgerodt, Felix
> Cc: Vignesh Balasubramanian ; linux-
> ker...@vger.kernel.org; linux-toolcha...@vger.kernel.org;
> m...@ellerman.id.au; npig...@gmail.com; christ
rnel.org; naveen.n@linux.ibm.com;
> ebied...@xmission.com; keesc...@chromium.org; x...@kernel.org; linuxppc-
> d...@lists.ozlabs.org; linux...@kvack.org; bpet...@amd.com;
> jinisusan.geo...@amd.com; m...@suse.de; binut...@sourceware.org;
> j...@freebsd.org; Willgerodt, Felix ; Vignesh
> Balasubram
xit+0x11/0x20 [amdgpu]
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Furthermore, I guess we are assuming that nobody is using the GPU when
the module is unloaded. As long as any processes have /dev/kfd open, you
won't be able to unl
n same core")
Signed-off-by: Randy Dunlap
Cc: Gautham R. Shenoy
Cc: Michael Ellerman
Cc: Nicholas Piggin
Cc: Christophe Leroy
Cc: linuxppc-dev@lists.ozlabs.org
Cc: amd-...@lists.freedesktop.org
Cc: Felix Kuehling
Cc: Alex Deucher
Cc: Christian König
Cc: "Pan, Xinhui"
Acked-by: Fel
esitant to post.
This is one of them.
What do people think about this?
Does it make sense to configure a UML kernel with a real device driver
in the first place? Or should we just prevent enabling amdgpu for UML
with a Kconfig dependency?
Regards,
Felix
thanks.
---
From: Randy Du
Am 2021-10-27 um 9:42 p.m. schrieb Alistair Popple:
> On Wednesday, 27 October 2021 3:09:57 AM AEDT Felix Kuehling wrote:
>> Am 2021-10-25 um 12:16 a.m. schrieb Alistair Popple:
>>> MIGRATE_PFN_LOCKED is used to indicate to migrate_vma_prepare() that a
>>> source pag
t;
> Signed-off-by: Alistair Popple
It makes sense to me. Do you have any empirical data on how much more
likely migrations are going to fail with this change due to contested
page locks?
Either way, the patch is
Acked-by: Felix Kuehling
> ---
> Documentation/vm/hmm.rst
On 2018-10-22 1:23 p.m., Arun KS wrote:
> Remove managed_page_count_lock spinlock and instead use atomic
> variables.
>
> Suggested-by: Michal Hocko
> Suggested-by: Vlastimil Babka
> Signed-off-by: Arun KS
Acked-by: Felix Kuehling
Regards,
Felix
>
> ---
>
On 31/08/2017 01:32, Sukadev Bhattiprolu wrote:
Michael Neuling [mi...@neuling.org] wrote:
Suka,
Please CC Christophe who as an alternative way of doing this. We ned to get
agreement across all users of TIDR/AS_notify...
Mikey,
Thanks. There is overlap between the two patches. I will send a p
regard:
1. How difficult would be to modify mainline UPM NAND driver to work
on MPC8260 ?
2. What other options are feasible and cost effective? I was thinking
about
SPI NOR and Compact Flash on UPM.
Thanks.
Felix.
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fter deep sleep.
With default implementation USB is dead on 85xx after deep sleep
if USB PHY is
powered down.
Felix.
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h default implementation USB is dead on 85xx after deep sleep
if USB PHY is
powered down completely.
Felix.
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Interrupt handler in MPC8xxx GPIO driver is missing the call
to PIC EOI (end of interrupt) handler. As a result, at least
on 85XX systems, GPIO interrupt is delivered only once. This
patch adds the missing EOI call. Tested on custom P1022 board.
Signed-off-by: Felix Radensky
---
arch/powerpc
line. If it's possible
on ARM, it should be doable on powerpc, right ?
Felix.
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Hi Grant,
On 09/27/2011 09:29 PM, Grant Likely wrote:
On Tue, Sep 27, 2011 at 04:59:28PM +0300, Felix Radensky wrote:
Hi,
Looks like 8xxx GPIO driver cannot properly handle interrupts
when multiple GPIO controllers exist in the system.
On Freescale P1022 there are 3 GPIO controllers. All 3
() is invoked
3 times with same hardware irq number. The result is interrupt
storm, mpc8xxx_gpio_irq_cascade() is invoked indefinitely.
What would be the best way to fix the problem ?
Thanks.
Felix Radensky.
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this approach is that GPIO IRQ cannot
be naturally specified in device tree by GPIO controller number
and GPIO pin number.
So what is the correct way to refer to 85XX GPIO IRQs in driver
code ?
Thanks.
Felix.
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Hi,
On 07/31/2011 04:59 PM, Tabi Timur-B04825 wrote:
Felix Radensky wrote:
What happens when I load my driver is single execution of interrupt
handler
followed by system freeze. Even if I call disable_irq() in interrupt
handler the
system still freezes.
I don't know any
Hi Wolfgang,
On 07/31/2011 08:49 PM, Wolfgang Grandegger wrote:
Hi Felix,
On 07/31/2011 05:51 PM, Felix Radensky wrote:
Hi Wolfgang,
On 07/31/2011 06:19 PM, Wolfgang Grandegger wrote:
On 07/31/2011 12:38 PM, Felix Radensky wrote:
Hi,
I'm running kernel 3.0 on a custom board bas
Hi Wolfgang,
On 07/31/2011 06:19 PM, Wolfgang Grandegger wrote:
On 07/31/2011 12:38 PM, Felix Radensky wrote:
Hi,
I'm running kernel 3.0 on a custom board based on Freescale P1022.
The interrupt line of on-board FPGA is connected to GPIO2_9. FPGA
IRQ is level, active low. The GPIOs are m
Hi Timur,
On 07/31/2011 04:59 PM, Tabi Timur-B04825 wrote:
Felix Radensky wrote:
What happens when I load my driver is single execution of interrupt
handler
followed by system freeze. Even if I call disable_irq() in interrupt
handler the
system still freezes.
I don't
e0/gpio-controller@f200 mapped to
virtual irq 31
mpc8xxx_irq_set_type: virq 9 flow_type 2
mpc8xxx_irq_unmask: irq 9
mpc8xxx_gpio_irq_cascade: irq 47
mpc8xxx_irq_mask: irq 9
mpc8xxx_irq_ack: irq 9
What am I doing wrong ?
Thanks a lot.
Felix.
_
On P1022DS both ethernet controllers are connected to RGMII PHYs
accessible via MDIO bus. Remove fixed-link property from ethernet
nodes as they only required when fixed link PHYs without MDIO bus
are used.
Signed-off-by: Felix Radensky
---
arch/powerpc/boot/dts/p1022ds.dts |2 --
1 files
Hi,
On 06/22/2011 08:12 PM, Felix Radensky wrote:
Hi Timur,
On 06/22/2011 07:18 PM, Timur Tabi wrote:
Felix Radensky wrote:
What am I doing wrong ?
Can you debug the PHY driver to see if it's getting called and
trying to talk to
the PHY itself?
I'll do that tomorrow and r
Hi Timur,
On 06/22/2011 07:18 PM, Timur Tabi wrote:
Felix Radensky wrote:
What am I doing wrong ?
Can you debug the PHY driver to see if it's getting called and trying to talk to
the PHY itself?
I'll do that tomorrow and report back.
Than
lt;&etsec1_clk>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
...
};
What
This patch extends NDFC driver to support all 4 chip selects
available in NDFC NAND controller. Tested on custom 460EX board
with 2 chip select NAND device.
Signed-off-by: Felix Radensky
---
I'd appreciate some testing on 44x boards with multiple NAND
devices, like bamboo or DU440, as I
Hi Poonam,
Thanks for the confirmation.
Felix.
On 04/15/2011 09:27 AM, Kushwaha Prabhakar-B32579 wrote:
Added Linxppc-dev
-Original Message-
From: Aggrwal Poonam-B10812
Sent: Friday, April 15, 2011 11:47 AM
To: Felix Radensky
Cc: Kushwaha Prabhakar-B32579; leon.woestenb...@gmail.com
y generate this situation with below commands:
I think Scott's patch was picked up by Artem Bityutskijy into his
tree, but never made it to mainline.
Felix.
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Hi Poonam
On 04/12/2011 07:05 AM, Aggrwal Poonam-B10812 wrote:
Hello Felix
Please find some comments inline.
Regards
Poonam
-Original Message-
From: Kushwaha Prabhakar-B32579
Sent: Tuesday, April 12, 2011 9:26 AM
To: Aggrwal Poonam-B10812
Subject: FW: Problem with mini-PCI-E slot on
Hi,
On 04/12/2011 07:35 AM, Benjamin Herrenschmidt wrote:
On Tue, 2011-04-12 at 04:05 +, Aggrwal Poonam-B10812 wrote:
May be you can look at
http://old.nabble.com/Problem-with-mini-PCI-E-slot-on-P2020RDB-td26802038.html
Felix we do not have the atheros driver for 2.6.38 and the issue is
t possible on such boards. The problem was
fixed in board revision D. To use legacy interrupts one has to modify
pci-e nodes in device tree and add "interrupt-map-mask" and
"interrupt-map" properties.
Do you agree with this analysis ?
Felix.
-Original Message-
From: F
Hi,
Assuming I have all patches in place, will this problem be
resolved on earlier board revisions (before rev D) ?
Felix.
On 04/11/2011 12:06 PM, Kushwaha Prabhakar-B32579 wrote:
Hi Fabe,
Yes .. P1020/P1011 RDB has same issue as of P2020RDB.
It was because of some missing patches at u-boot
Hi Leon,
On 04/06/2011 11:58 PM, Leon Woestenberg wrote:
Hello Felix,
On Wed, Apr 6, 2011 at 10:49 PM, Felix Radensky wrote:
I think there's a hardware problem with mini PCI-E slot
on P2020RDB related to legacy IRQ routing. See this
thread for details
http://www.mail-archive.com/linuxpp
Hi Leon,
I think there's a hardware problem with mini PCI-E slot
on P2020RDB related to legacy IRQ routing. See this
thread for details
http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg40037.html
You may have better luck with PCI-E slot and mini PCI-E to
PCI-E adapter.
Hi Ira,
I've successfully tested this version on P2020RDB,
with 10 threads per channel, 10 iterations per
thread.
Tested-by: Felix Radensky
Felix.
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ying dest buffer...
dma0chan0-copy0: #3: No errors with src_off=0x4ff dst_off=0x453 len=0x395d
dma0chan0-copy0: terminating after 4 tests, 0 failures (status 0)
Felix.
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Hi Ira,
On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
Hi Ira,
Thank you very much Felix. The dmesg output
Hi Ira,
On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
Hi Ira,
Thank you very much Felix. The dmesg output
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
Hi Ira,
Thank you very much Felix. The dmesg output shows that the controller
never got an interrupt for the second transaction. The patch below has
extra debugging
Hi Ira,
Thank you very much Felix. The dmesg output shows that the controller
never got an interrupt for the second transaction. The patch below has
extra debugging information that may help determine why this happens.
Please apply it and re-run the test.
The last section of dmesg (after
Hi Ira,
Attached dmesg output.
Felix.
Original Message
Subject:
Re: [PATCH 0/8] fsldma: lockup fixes
Date:
Mon, 28 Feb 2011 09:16:24 -0800
be dmatest threads_per_chan=2 iterations=1
Felix.
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Hi Ira,
On 01/25/2011 06:29 PM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 04:32:02PM +0200, Felix Radensky wrote:
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder
Hi Ira,
On 01/25/2011 02:18 AM, Ira W. Snyder wrote:
On Tue, Jan 25, 2011 at 01:39:39AM +0200, Felix Radensky wrote:
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to pe
Hi Ira, Scott
On 01/25/2011 12:26 AM, Ira W. Snyder wrote:
On Mon, Jan 24, 2011 at 11:47:22PM +0200, Felix Radensky wrote:
Hi,
I'm trying to use FSL DMA engine to perform DMA transfer from
memory buffer obtained by kmalloc() to PCI memory. This is on
custom board based on P2020 running
rc = -EIO;
}
return rc;
}
The destination address is PCI memory address returned by
pci_ioremap_bar().
The transfer silently fails, destination buffer doesn't change
contents, but no
error condition is reported.
What am I doing wrong ?
Thanks a lot in advance.
Felix.
Hi Timur,
There are currently no drivers in mainline for FSL eSPI controller and eSPI
flash.
They are present only in FSL BSP kernel. Do you think it makes sense to keep
DTS entries for something that is not supported ?
Felix.
On 7/3/2010 1:25 AM, Timur Tabi wrote:
Introduce basic support
Hi Kumar,
On 5/11/2010 3:36 PM, Kumar Gala wrote:
On May 10, 2010, at 2:15 PM, Felix Radensky wrote:
Fix legacy PCI-E interrupt mapping for PCI-E slot 0 of
P2020DS evaluation board. The patch is based on P2020DS
device tree from Freescale BSP for this board.
Signed-off-by: Felix Radensky
Fix legacy PCI-E interrupt mapping for PCI-E slot 0 of
P2020DS evaluation board. The patch is based on P2020DS
device tree from Freescale BSP for this board.
Signed-off-by: Felix Radensky
---
arch/powerpc/boot/dts/p2020ds.dts |8
1 files changed, 4 insertions(+), 4 deletions
hanks.
Felix.
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/gpp/kernel-2.6.32-rc3-P1020RDB-DTS-Support-for-eTSEC-2.0-v0.patch
but revamped for the mainline's OF bindings.
Thanks a lot, I appreciate your help.
Felix.
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Hi Kumar,
On 4/9/2010 8:43 AM, Kumar Gala wrote:
On Apr 8, 2010, at 5:53 AM, Felix Radensky wrote:
Hi,
I've just noticed that ethernet nodes are missing in p1020rdb device tree.
Are there any known problems with ethernet controllers on p1020rdb ?
I'd say its not pro
Hi,
I've just noticed that ethernet nodes are missing in p1020rdb device tree.
Are there any known problems with ethernet controllers on p1020rdb ?
Thanks.
Felix.
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Hello Kenji-san,
Kenji Kaneshige wrote:
Felix, I think assigning hpXXsize at boot time is the simpler solution,
if it is acceptable workaround for you. And as Yinghai suggested in the
another email, removing slot's parent bridge first should be one of the
workaround. But the probl
Hi Ben,
Benjamin Herrenschmidt wrote:
On Sun, 2010-03-28 at 12:13 +0300, Felix Radensky wrote:
I've tried Jesse's tree with Yinghai's patches, but they don't seem to help.
Memory for bridge is not allocated after insertion of hotplug device and
bus rescan. Attached dme
Hello, Kenji-san
Kenji Kaneshige wrote:
Felix Radensky wrote:
Hello, Kenji-san
Kenji Kaneshige wrote:
I misunderstood the problem.
My understanding was memory resource was not enabled even though
Linux set
the Memory Space bit in the command register. But it was not
correct. The
bridge
Hi Ben,
Benjamin Herrenschmidt wrote:
On Wed, 2010-03-17 at 09:38 +0200, Felix Radensky wrote:
Hello Kenj-san
Kenji Kaneshige wrote:
By the way, I think Yinghai's bridge resource reallocation patch series
might help you. It is in Jesse's PCI tree. Please take a look.
oth cases the kernel doesn't boot unless PCI support is
disabled. Debugging is difficult as the board just resets before
anything is
is printed on console.
Felix.
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passing
hpmemsize
kernel parameter, to specify the amount of memory to assign to the bridge.
I've tested this approach and it seems to work.
Thanks.
Felix.
Felix.
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ing all
configuration itself. But both u-boot
and linux do not assign memory resources to bridge if there's no device
behind it.
Thanks a lot.
Felix.
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e software that I don't really want to modify
heavily.
But I'll do that if generic PCI rescan cannot be fixed.
Thanks a lot for your help.
Felix.
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Hello Kenji-san,
Kenji Kaneshige wrote:
Felix Radensky wrote:
Hello Kenji-san,
Kenji Kaneshige wrote:
I'm not sure, but I guess pci_setup_bridge() didn't update IO
base/limit
and Mem base/limit of the bridge (:00:02.0) because of the
following
lines.
static void pci_se
ory window is properly allocated.
For some reason bridge memory is disabled, but if I enable it via
setpci, and
also enable device memory, then everything works fine. If the system is
booted
when device behind the bridge is plugged in, bridge memory is en
NUM# interrupt, but
Hotswap Control register layout does not completely follow the standard.
Should I use drivers/pci/hotplug/cpci_hotplug_core.c as a base, or do
you have
something more simple in mind ?
Thanks a lot.
Felix.
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Hi Alex,
Thanks a lot for replying.
Alex Chiang wrote:
* Felix Radensky :
The problem arises when device is plugged in after boot. After doing
echo 1 > /sys/bus/pci/rescan
the device is identified, but bridge memory window is not allocated,
and reads from device memory regi
Hi Alex,
Resending, previous attempt was erroneously send as HTML.
Thanks a lot for replying.
Alex Chiang wrote:
* Felix Radensky :
The problem arises when device is plugged in after boot. After doing
echo 1 > /sys/bus/pci/rescan
the device is identified, but bridge memory window is
Thanks a lot.
Felix.
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leave core1 in
reset, start Linux on core0 from u-boot and load bare metal application
from Linux. If this
possible, where can I learn about the procedure ?
Thanks.
Felix.
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Hi, Stef
Benjamin Herrenschmidt wrote:
On Wed, 2010-01-20 at 00:52 +0200, Felix Radensky wrote:
405XX - no
440EP - no
440GR - no
440EPx/440GRx - no
440GP - yes
440GX - yes
440SP - yes
440SPe - yes
460XX - yes
The distinction between these groups is pretty clear in the device trees.
The
40SPe - yes
460XX - yes
The distinction between these groups is pretty clear in the device trees.
The members of the first group all have "ibm,plb-pci" property, and all
members of second group have "ibm,plb-pcix" property.
So onl
Hi Ben
Benjamin Herrenschmidt wrote:
On Tue, 2010-01-12 at 00:48 +0200, Felix Radensky wrote:
Maybe because the bus behind root P2P bridge is bus 0, and type 1
cycles are
needed for bus numbers greater than 0. That's what 460EX manual says.
Well, no... the bus behind the root P
ef's fix. I
don't have access to a
system with devices behind PLX, and the guy who did the testing used
wrong kernel.
I'll make sure he uses the correct one and get back to you. Maybe
everything works after all :)
I'm really sorry for confusion.
Felix.
__
Hi Stef
Felix Radensky wrote:
Hi Stef,
Stef van Os wrote:
Hello Felix,
I had a problem similar to this on the 440GX, the PCI code was not
sending type 1 transactions when scanning behind bridges. Perhaps you
could try this:
Index: linux/arch/powerpc/sysdev/ppc4xx_pci.c
Hi Stef,
Stef van Os wrote:
Hello Felix,
I had a problem similar to this on the 440GX, the PCI code was not
sending type 1 transactions when scanning behind bridges. Perhaps you
could try this:
Index: linux/arch/powerpc/sysdev/ppc4xx_pci.c
Benjamin Herrenschmidt wrote:
On Sun, 2010-01-10 at 14:56 +0200, Felix Radensky wrote:
I now have a custom board with 460EX and the same PLX bridge, running
2.6.23-rc3
Things look better here, as u-boot is now able to properly detect PLX
and device behind
it, but kernel still has problems
Hi, Ben
Felix Radensky wrote:
Hi, Ben
Adding Feng Kan from AMCC to CC.
Benjamin Herrenschmidt wrote:
On Mon, 2009-12-28 at 12:51 +0200, Felix Radensky wrote:
Hi,
I'm running linux-2.6.33-rc2 on Canyonlands board. When PLX 6254
transparent PCI-PCI
bridge is plugged into PCI slo
Hi, Ben
Adding Feng Kan from AMCC to CC.
Benjamin Herrenschmidt wrote:
On Mon, 2009-12-28 at 12:51 +0200, Felix Radensky wrote:
Hi,
I'm running linux-2.6.33-rc2 on Canyonlands board. When PLX 6254
transparent PCI-PCI
bridge is plugged into PCI slot the kernel simply resets the
in this thread:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2008-October/063939.html
I'd appreciate any help in resolving this issue. Below is dmesg output
with DEBUG enabled
and problematic test for broken removed.
Using PowerPC 44x Platform machine description
Linux version 2.6.
Hi, Wolfgang
Wolfgang Grandegger wrote:
Felix Radensky wrote:
Hi, Wolfgang
Wolfgang Grandegger wrote:
Felix Radensky wrote:
Hi,
Almost all MPC85XX based systems have the compatible=:"fsl-i2c" in
respective
i2c device tree nodes. This causes FSL i2c driver
Hi, Wolfgang
Wolfgang Grandegger wrote:
Felix Radensky wrote:
Hi,
Almost all MPC85XX based systems have the compatible=:"fsl-i2c" in
respective
i2c device tree nodes. This causes FSL i2c driver to use the following
"backward
compatible" values: FSR=0x31 DFSR=0x10. This
s this the right approach ?
Thanks.
Felix.
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obody cared"
message when driver executes request_irq(). Vivek has come to a
conclusion that the problem is
related to incorrect IRQ0 routing for mini-PCI-E slot on P2020RDB.
Felix.
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Mahajan Vivek-B08308 wrote:
From:
linuxppc-dev-bounces+vivek.mahajan=freescale@lists.ozlabs.
org
[mailto:linuxppc-dev-bounces+vivek.mahajan=freescale@lists
.ozlabs.org] On Behalf Of Felix Radensky
Sent: Thursday, December 17, 2009 12:52 PM
I just noticed a MSI enable bit in
t to the driver is not
trivial.
They've tried once, it didn't work and they gave up. Any chance I can use
mini-PCI-E slot without MSI ?
Thanks.
Felix.
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Mahajan Vivek-B08308 wrote:
From: Felix Radensky [mailto:fe...@embedded-sol.com]
Sent: Wednesday, December 16, 2009 2:56 PM
To: Mahajan Vivek-B08308
Cc: linuxppc-...@ozlabs.org; Aggrwal Poonam-B10812; Kumar Gala
Subject: Re: Problem with mini-PCI-E slot on P2020RDB
Hi,
Looks like INTA is
ic 0x1 0x1
0x0 0x0 0x2 &mpic 0x2 0x1
0x0 0x0 0x3 &mpic 0x3 0x1
0x0 0x0 0x4 &mpic 0x0 0x1
Thanks for your help. With this change "nobody cared" message disappears,
but interrupts are not coming at all.
Is it a
os card plugged into regular PCI-E slot works OK in FSL BSP.
Any help in resolving this is much appreciated.
Thanks.
Felix.
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Hi,
Michael Chan wrote:
On Thu, 2009-11-19 at 08:08 -0800, Felix Radensky wrote:
Hi,
The problem goes away if I remove the call to
tg3_set_power_state(tp, PCI_D3hot);
from tg3_close().
Added Matt to CC. He is on vacation and may not be able to look into
this right away. Thanks
trl[7618] dma_mask[64-bit]
Is my problem related to hardware or it's a tg3 driver bug ?
Thanks a lot.
Felix.
Felix Radensky wrote:
Hi,
I have a problem with tg3 driver on a custom MPC8536 based board
running linux-2.6.31, with tg3 and Broadcom phy drivers taken from
linux-2.6.32-rc7.
comes back.
Am I the only one seeing this problem ?
Any help on fixing this is appreciated.
Thanks a lot.
Felix.
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to be no way do pass ENUM# irq
number into the driver. How should one define ENUM# interrupt in
device tree ?
Thanks a lot in advance.
Felix.
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Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed
Scott Wood wrote:
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex wit
Scott Wood wrote:
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex wit
Scott Wood wrote:
On Sun, Oct 18, 2009 at 11:38:13AM +0200, Felix Radensky wrote:
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed
Hi, Scott
Scott Wood wrote:
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard
Hi, Norbert
Norbert van Bolhuis wrote:
Hi Felix,
do you have CONFIG_NO_HZ defined ?
I've seen similar problems with powerpc + CONFIG_NO_HZ. In my case the
low-level
do_write_buffer (cfi_cmdset_0002.c) timed out too early. See
http://lkml.org/lkml/2009/9/3/84
Maybe in your case it&
Hi, Scott
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of
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