up to match the BDF/PASID of the AFU.
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
index
determine when the TLB Invalidate
has been completed.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 51
arch/powerpc/platforms/powernv/ocxl.c | 69 +++
2 files changed, 120 insertions(+)
diff --git a/arch/powerpc
Add specific kernel traces which provide information on mmu notifier and on
pages range.
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 4 +++
drivers/misc/ocxl/trace.h | 64 +++
2 files changed, 68 insertions
r the time being, the ATSD0 set of registers is used by default.
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 3 ++
arch/powerpc/platforms/powernv/ocxl.c | 45 +++
2 files changed, 48 insertions(+)
diff --git a/ar
Reserved
6
Acked-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/context.c | 4 +++-
drivers/misc/ocxl/link.c | 4 +++-
drivers/misc/ocxl/ocxl_internal.h | 9 ++---
drivers/scsi/cxlflash/ocxl_hw.c | 6 --
include
PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
Changelog[v4]
- Rebase to latest upstream.
- Correct a typo in page size
Changelog[v3]
- Rebase to latest upstream.
- Add page_size
Le 24/11/2020 à 14:45, Jason Gunthorpe a écrit :
On Tue, Nov 24, 2020 at 09:17:38AM +, Christoph Hellwig wrote:
@@ -470,6 +487,26 @@ void ocxl_link_release(struct pci_dev *dev, void
*link_handle)
}
EXPORT_SYMBOL_GPL(ocxl_link_release);
+static void invalidate_range(struct mmu_notif
Add specific kernel traces which provide information on mmu notifier and on
pages range.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 4 +++
drivers/misc/ocxl/trace.h | 64 +++
2 files changed, 68 insertions(+)
diff --git a/drivers/misc
r the time being, the ATSD0 set of registers is used by default.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 3 ++
arch/powerpc/platforms/powernv/ocxl.c | 45 +++
2 files changed, 48 insertions(+)
diff --git a/arch/powerpc/include/asm/pnv
PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
Changelog[v3]
- Rebase to latest upstream.
- Add page_size argument in pnv_ocxl_tlb_invalidate()
- Remove double pointer
Changelog[v2
determine when the TLB Invalidate
has been completed.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 51 +++
arch/powerpc/platforms/powernv/ocxl.c | 70 +++
2 files changed, 121 insertions(+)
diff --git a/arch/powerpc
up to match the BDF/PASID of the AFU.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
index 77381dda2c45..129d4eddc4d2
Reserved
6
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/context.c | 4 +++-
drivers/misc/ocxl/link.c | 4 +++-
drivers/misc/ocxl/ocxl_internal.h | 9 ++---
drivers/scsi/cxlflash/ocxl_hw.c | 6 --
include/misc/ocxl.h | 2
determine when the TLB Invalidate
has been completed.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 50
arch/powerpc/platforms/powernv/ocxl.c | 55 +++
2 files changed, 105 insertions(+)
diff --git a/arch
Add specific kernel traces which provide information on mmu notifier and on
pages range.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 4 +++
drivers/misc/ocxl/trace.h | 64 +++
2 files changed, 68 insertions(+)
diff --git a/drivers/misc
up to match the BDF/PASID of the AFU.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/link.c | 58 +++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
index 20444db8a2bb..100bdfe9ec37
Reserved
6
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/context.c | 4 +++-
drivers/misc/ocxl/link.c | 4 +++-
drivers/misc/ocxl/ocxl_internal.h | 4 +++-
drivers/scsi/cxlflash/ocxl_hw.c | 6 --
include/misc/ocxl.h | 2
PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
Changelog[v2]
- Rebase to latest upstream.
- Create a set of smaller patches
- Move the device tree parsing and ioremap() for the
r the time being, the ATSD0 set of registers is used by default.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 3 ++
arch/powerpc/platforms/powernv/ocxl.c | 48 +++
2 files changed, 51 insertions(+)
diff --git a/arch/powerpc/include/asm/pnv
commands from the PowerBus.
The Shootdown commands (ATSD) will be generated using MMIO registers
in the NPU/PAU and sent to the device.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 2 +
arch/powerpc/platforms/powernv/ocxl.c | 19 +++
drivers/misc/ocxl/link.c
On 05/11/2019 06:01, Andrew Donnellan wrote:
On 22/10/19 6:52 pm, christophe lombard wrote:
Fix up the pci config size of the OpenCAPI PCIe devices in the pseries
environment.
Most of OpenCAPI PCIe devices have 4096 bytes of configuration space.
It's not "most of", it's
On 22/10/2019 09:52, christophe lombard wrote:
pseries.c implements the guest-specific callbacks for the backend API.
The hypervisor calls provide an interface to configure and interact with
OpenCAPI devices. It matches the last version of the 'PAPR changes'
document.
The following
value, requested to configure the process element in the
Scheduled Process Area, is not available in the QEMU environment.
This implies getting it from the host through the iommu group.
Signed-off-by: Christophe Lombard
---
drivers/vfio/pci/Kconfig | 7 +
drivers/vfio/pci/Makefile
=0007:00:00.0,addr=2.0 -device
vfio-pci,multifunction=on,host=0007:00:00.1,addr=2.1
It has been tested in a bare-metal and QEMU environment using the memcpy
and the AFP AFUs.
christophe lombard (2):
powerpc/powernv: Register IOMMU group for OpenCAPI devices
vfio/pci: Introduce OpenCAPI devices s
ch is common for each
devices sharing the same domain, same bus and same slot.
Signed-off-by: Christophe Lombard
---
arch/powerpc/platforms/powernv/ocxl.c | 164 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 19 ++-
arch/powerpc/platforms/powernv/pci.h | 13 ++
3
meters are common to all hcalls (buid and config_addr) that will
be used to allow QEMU to recover the PCI device.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/Makefile| 1 +
drivers/misc/ocxl/main.c | 4 +
drivers/misc/ocxl/ocxl_internal.h | 1 +
drivers/misc/ocxl
describe
their own definition. See struct ocxl_backend_ops.
It has been tested in a bare-metal and QEMU environment using the memcpy and
the AFP AFUs.
christophe lombard (3):
ocxl: Introduce implementation-specific API
ocxl: Add pseries-specific code
powerpc/pseries: Fixup config space size of
Fix up the pci config size of the OpenCAPI PCIe devices in the pseries
environment.
Most of OpenCAPI PCIe devices have 4096 bytes of configuration space.
Signed-off-by: Christophe Lombard
---
arch/powerpc/platforms/pseries/pci.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch
the pnv_ocxl_ API for the
bare-metal environment.
Signed-off-by: Christophe Lombard
---
drivers/misc/ocxl/Makefile| 2 +
drivers/misc/ocxl/config.c| 7 ++-
drivers/misc/ocxl/link.c | 31 +--
drivers/misc/ocxl/main.c | 5 ++
drivers/misc/ocxl
.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 46 ++--
arch/powerpc/platforms/powernv/ocxl.c | 297 +---
drivers/misc/ocxl/afu_irq.c | 1 -
drivers/misc/ocxl/link.c | 383 +++---
drivers/misc/ocxl
: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 6 +-
arch/powerpc/platforms/powernv/ocxl.c | 103 --
drivers/misc/ocxl/config.c| 89 +-
3 files changed, 99 insertions(+), 99 deletions(-)
diff --git a/arch/powerpc/include/asm
d the
entry in the SPA. (Fred)
christophe lombard (2):
powerpc/powernv: ocxl move SPA definition
powerpc/powernv: ocxl move TL definition
arch/powerpc/include/asm/pnv-ocxl.h | 46 +--
arch/powerpc/platforms/powernv/ocxl.c | 400 +++---
drivers/misc/ocxl/afu_
On 14/10/2019 12:21, Frederic Barrat wrote:
Le 09/10/2019 à 17:11, christophe lombard a écrit :
Specifies the templates in the Transaction Layer that the OpenCAPI
device/host
support when transmitting/receiving DL/DLX frames to or from the OpenCAPI
device/host.
Update, rename and create new
On 14/10/2019 12:17, Frederic Barrat wrote:
diff --git a/arch/powerpc/platforms/powernv/ocxl.c
b/arch/powerpc/platforms/powernv/ocxl.c
index 8c65aacda9c8..4d26cba12b63 100644
--- a/arch/powerpc/platforms/powernv/ocxl.c
+++ b/arch/powerpc/platforms/powernv/ocxl.c
@@ -12,11 +12,54 @@
#define P
On 11/10/2019 10:06, christophe lombard wrote:
On 11/10/2019 00:34, Andrew Donnellan wrote:
On 10/10/19 2:11 am, christophe lombard wrote:
This series moves the definition and the management of scheduled
process area
(SPA) and of the templates (Transaction Layer) for an ocxl card,
using the
On 11/10/2019 00:34, Andrew Donnellan wrote:
On 10/10/19 2:11 am, christophe lombard wrote:
This series moves the definition and the management of scheduled
process area
(SPA) and of the templates (Transaction Layer) for an ocxl card, using
the
OCAPI interface. The code is now located in the
: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 5 +-
arch/powerpc/platforms/powernv/ocxl.c | 103 --
drivers/misc/ocxl/config.c| 89 +-
3 files changed, 99 insertions(+), 98 deletions(-)
diff --git a/arch/powerpc/include/asm
create new few platform-specific calls which can be used by
drivers.
No functional change.
Signed-off-by: Christophe Lombard
---
arch/powerpc/include/asm/pnv-ocxl.h | 25 +-
arch/powerpc/platforms/powernv/ocxl.c | 275 ++--
drivers/misc/ocxl/afu_irq.c | 1 -
drivers
metal environment using the memcpy and
the AFP AFUs.
christophe lombard (2):
powerpc/powernv: ocxl move SPA definition
powerpc/powernv: ocxl move TL definition
arch/powerpc/include/asm/pnv-ocxl.h | 30 +-
arch/powerpc/platforms/powernv/ocxl.c | 378 +++---
drivers/misc
tch sounds good. Thanks.
Reviewed-by: Christophe Lombard
branch that
checks for not null AFU pointer in 'adapter->slices' [Fred]
* Removed a misleading comment in code.
---
Thanks
Acked-by: Christophe Lombard
On 25/01/2019 06:11, Vaibhav Jain wrote:
Recent updates to OPAL [1] have provided support for new CXL modes on
PHB that need to force a cold reset on the bridge (CRESET). However
PHB CRESET is a multi step process and cannot be completed
synchronously as expected by current kernel implementation
the access to the AFU Descriptor Data indexed by the
AFU Info Index field.
Fixes: 5ef3166e8a32 ("ocxl: Driver code for 'generic' opencapi devices")
Cc: stable # 4.16
Signed-off-by: Christophe Lombard
Acked-by: Frederic Barrat
Acked-by: Andrew Donnellan
---
Changelog[
Le 14/08/2018 à 05:26, Michael Ellerman a écrit :
Hi Christophe,
The patch looks fine, just a nit about the change log:
Christophe Lombard writes:
The AFU Information DVSEC capability is a means to extract common,
general information about all of the AFUs associated with a Function
.
Fixes: 5ef3166e8a32 ("ocxl: Driver code for 'generic' opencapi devices")
Cc: stable # 4.16
Signed-off-by: Christophe Lombard
---
Changelog[v2]
- Rebase to latest upstream.
- Use pci_write_config_byte instead of pci_write_config_word
---
drivers/misc/ocxl/config.c | 4 +++
Le 13/08/2018 à 11:48, Andrew Donnellan a écrit :
On 13/08/18 19:01, Christophe Lombard wrote:
From: Christophe Lombard
Your git committer email should probably match your sign-off email.
The AFU Information DVSEC capability is a means to extract common,
general information about all of
From: Christophe Lombard
The AFU Information DVSEC capability is a means to extract common,
general information about all of the AFUs associated with a Function
independent of the specific functionality that each AFU provides.
This patch fixes the access to the AFU Descriptor Data indexed by
Le 24/03/2018 à 09:14, Benjamin Herrenschmidt a écrit :
On Fri, 2018-03-23 at 17:17 +0100, christophe lombard wrote:
Le 23/03/2018 à 03:14, Benjamin Herrenschmidt a écrit :
On Thu, 2018-03-22 at 17:37 +0100, Christophe Lombard wrote:
The cxl driver cannot disable the interrupt at the device
chines are disabled
*/
- cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x000100102A10ULL);
+ cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x000100112A10ULL);
/*
* A response to an ASB_Notify request is returned by the
Thanks
Reviewed-by: Christophe Lombard
lue any longer. This
patch modifies the cxl driver to set/reset the Tunnel BAR register when
entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar().
Signed-off-by: Philippe Bergheaud
---
Thanks
Reviewed-by: Christophe Lombard
Le 23/03/2018 à 03:14, Benjamin Herrenschmidt a écrit :
On Thu, 2018-03-22 at 17:37 +0100, Christophe Lombard wrote:
The cxl driver cannot disable the interrupt at the device level and has
to use disable_irq[_nosync] instead.
To avoid the implementation of the lazy optimisation (the interrupt
'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/guest.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/guest.c b/drivers/misc/cxl/guest.c
index f58b4b6c..dc476e1 100644
--- a/drivers/misc/cxl/guest.c
+++ b/driver
when a page fault is handle
through cxllib.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxllib.c | 3 ++
drivers/misc/cxl/fault.c | 2 +
drivers/misc/cxl/irq.c| 2 +-
drivers/misc/cxl/trace.h | 115 ++
4 files changed, 72 inserti
tex before setting the phb indications.
v7: get_phb_indications():
cxl_get_xsl9_dsnctl():
- return -ENODEV instead of -1.
v8: get_phb_indications():
- stay on the safe side: acquire the mutex unconditionally
v9,v10: No change.
---
Reviewed-by: Christophe Lombard
pal call numbers to their final values.
---
Reviewed-by: Christophe Lombard
Le 21/02/2018 à 03:43, Michael Ellerman a écrit :
Christophe Lombard writes:
The PSL Timebase register is updated by the PSL to maintain the
timebase.
On P9, the Timebase value is only provided by the CAPP as received
the last time a timebase request was performed.
The timebase requests are
sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
now dynamically updated according the content of the PSL Timebase
register.
Signed-off-by: Christophe Lombard
Reviewed-by: Vaibhav Jain
Acked-by: Andrew Donnellan
---
This patch applies on top of this patch:
http://patchwork.
sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
now dynamically updated according the content of the PSL Timebase
register.
Signed-off-by: Christophe Lombard
---
This patch applies on top of this patch:
http://patchwork.ozlabs.org/patch/873663/
Changelog[v5]
- Rebased
sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
now dynamically updated according the content of the PSL Timebase
register.
Signed-off-by: Christophe Lombard
---
This patch applies on top of this patch:
http://patchwork.ozlabs.org/patch/873663/
Changelog[v4]
- Rebased
Le 19/02/2018 à 07:10, Vaibhav Jain a écrit :
Hi Christophe,
Mostly ok with this patch. Some very minor review comments:
Christophe Lombard writes:
--- a/drivers/misc/cxl/sysfs.c
+++ b/drivers/misc/cxl/sysfs.c
@@ -62,6 +62,16 @@ static ssize_t psl_timebase_synced_show(struct device
*device
sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
now dynamically updated according the content of the PSL Timebase
register.
Signed-off-by: Christophe Lombard
---
This patch applies on top of this patch:
http://patchwork.ozlabs.org/patch/873663/
Changelog[v3]
- Rebased
sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
now dynamically updated according the content of the PSL Timebase
register.
Signed-off-by: Christophe Lombard
---
Changelog[v2]
- Missing Signed-off-by
- Spaces required around the ':'
---
drivers/m
The PSL Timebase register is updated by the PSL to maintain the
timebase.
On P9, the Timebase value is only provided by the CAPP as received
the last time a timebase request was performed.
The timebase requests are initiated through the adapter configuration or
application registers.
The specific s
Le 11/02/2018 à 18:10, Vaibhav Jain a écrit :
Thanks for reviewing the patch Christophe,
christophe lombard writes:
+bool cxl_enable_psltrace = true;
+module_param_named(enable_psltrace, cxl_enable_psltrace, bool, 0600);
+MODULE_PARM_DESC(enable_psltrace, "Set PSL traces on probe. defaul
Le 09/02/2018 à 05:25, Vaibhav Jain a écrit :
We introduce a new module parameter named 'enable_psltrace' which asks cxl
to start(by default) psl-traces on an adapter as soon as its probe is
finished. In case this default behavior is not needed then this
module parameter can be set to '0'.
Signe
Le 09/02/2018 à 05:25, Vaibhav Jain a écrit :
We introduce a new enum named cxl_psl9_traceid that represents
individual trace-arrays available on PSL9. In addition a set of new
defines named s CXL_PSL9_TRACESTATE_XXX are introduced that represent
various states a trace-array can be in. Value of e
_psl9() and its
references from the code.
Signed-off-by: Vaibhav Jain
---
drivers/misc/cxl/pci.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
Reviewed-by: Christophe Lombard
apter, CXL_PSL9_DEBUG, 0xC000ULL);
+ }
return 0;
}
Reviewed-by: Christophe Lombard
les changed, 118 insertions(+), 9 deletions(-)
Acked-by: Christophe Lombard
ions(+), 7 deletions(-)
Acked-by: Christophe Lombard
the current thread which
will be used in the process element entry.
Signed-off-by: Christophe Lombard
Reviewed-by: Philippe Bergheaud
---
Changelog[v7]
- Rebased to latest upstream.
- Added boolean: "need to allocate a TIDR"
- Released the mutex and mark the context as STARTED in cas
the current thread which
will be used in the process element entry.
Signed-off-by: Christophe Lombard
Reviewed-by: Philippe Bergheaud
---
Changelog[v6]
- Rebased to latest upstream.
- Updated the ioctl interface.
- Removed the updated ptrace.
- Assigned a unique TIDR for the current thread at
the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported, instead of handling PVR values.
Signed-off-by: Christop
Le 20/12/2017 à 09:46, Vaibhav Jain a écrit :
Hi Chritophe,
christophe lombard writes:
Le 20/12/2017 à 07:31, Vaibhav Jain a écrit :
EINVAL might be a better return value instead of ENODEV in this case.
This return code has been already discussed (with mpe) on the first
version of the
Le 20/12/2017 à 07:31, Vaibhav Jain a écrit :
Hi Christophe,
Thanks for the changes to the patch. Few minor review comments:
Thanks for the review.
Christophe Lombard writes:
@@ -362,3 +363,17 @@ void cxl_context_mm_count_put(struct cxl_context *ctx)
if (ctx->
the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported, instead of handling PVR values.
Signed-off-by: Christop
the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported, instead of handling PVR values.
Signed-off-by: Christop
Add support for future Coherent Accelerator device with an
ID of 0x060e.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 19969ee..5f5b9aa 100644
--- a/drivers/misc/cxl/pci.c
the current thread which
will be used in the process element entry.
A next patch will handle a new kind of "compatible" property in the
device-tree (PHB DT node) indicating which version of CAPI and which
features are supported.
Signed-off-by: Christophe Lombard
---
Changelog[v2]
-
tch shouldn't impact the calling convention of set_thread_tidr()
i.e all -ve return-values are error codes and a return value of '0'
indicates success.
Fixes: ec233ede4c86("powerpc: Add support for setting SPRN_TIDR")
Signed-off-by: Vaibhav Jain
---
sounds good for me
T
Le 27/11/2017 à 05:03, Michael Ellerman a écrit :
christophe lombard writes:
Le 24/11/2017 à 14:02, Benjamin Herrenschmidt a écrit :
On Fri, 2017-11-24 at 11:14 +0100, christophe lombard wrote:
To my knowledge, there is no property (or similar), somewhere, that
indicating that the TIDR is
Le 24/11/2017 à 14:02, Benjamin Herrenschmidt a écrit :
On Fri, 2017-11-24 at 11:14 +0100, christophe lombard wrote:
To my knowledge, there is no property (or similar), somewhere, that
indicating that the TIDR is supported or not.
For the time being, if I am not wrong, the only check we have
Le 23/11/2017 à 21:41, Benjamin Herrenschmidt a écrit :
On Thu, 2017-11-23 at 12:05 +0100, Christophe Lombard wrote:
The POWER9 core supports a new feature: ASB_Notify which requires the
support of the Special Purpose Register: TIDR.
The ASB_Notify command, generated by the AFU, will attempt
Le 23/11/2017 à 15:16, Vaibhav Jain a écrit :
Hi Christophe,
Few review comments:
Christophe Lombard writes:
+
+int cxl_context_thread_tidr(struct cxl_context *ctx, int assign)
+{
+ int rc = 0;
+
+ /* Clear any TIDR value assigned to the current thread */
+ if (!assign
the current thread which
will be used in the process element entry.
Signed-off-by: Christophe Lombard
---
arch/powerpc/kernel/process.c | 2 ++
drivers/misc/cxl/api.c| 9 +
drivers/misc/cxl/context.c| 21 +
drivers/misc/cxl/cxl.h| 6 ++
drivers
://patchwork.ozlabs.org/patch/829294/
[1/2] phb4: set PHB CMPM registers for tunneled operations
https://patchwork.ozlabs.org/patch/829293/
[2/2] phb4: set PBCQ Tunnel BAR for tunneled operations
Looks good for me.
Acked-by: Christophe Lombard
Thanks
c/cxl/pci.c | 38 ++
3 files changed, 42 insertions(+), 32 deletions(-)
Thanks
Acked-by: Christophe Lombard
-> As created a different function to dump the FIR register for PSL9 (Fred)
---
Thanks
Acked-by: Christophe Lombard
: Frederic Barrat
Signed-off-by: Vaibhav Jain
Thanks
Acked-by: Christophe Lombard
: Frederic Barrat
Signed-off-by: Vaibhav Jain
---
Thanks
Acked-by: Christophe Lombard
Le 26/09/2017 à 03:44, Vaibhav Jain a écrit :
Hi Christophe,
A minor nitpick
Christophe Lombard writes:
+ for (dar = (addr & ~(page_size - 1)); dar < (addr + size); dar +=
page_size) {
+ if (dar < vma->vm_start || dar > vma->vm_end) {
Code commen
uched, and the address the
adapter is trying to access is never sent to the kernel for resolution.
This patch reworks start address of the loop with an address aligned on
the page size. In this context, the last page is not missed.
Signed-off-by: Christophe Lombard
Acked-by: Frederic Barrat
uched, and the address the
adapter is trying to access is never sent to the kernel for resolution.
This patch reworks start address of the loop with an address aligned on
the page size. In this context, the last page is not missed.
Signed-off-by: Christophe Lombard
Fixes: 3ced8d730063 (&q
he adapter is trying to access is never
sent to the kernel for resolution.
This patch updates the loop on the memory pages to be handled.
Signed-off-by: Christophe Lombard
Fixes: 3ced8d730063 ("cxl: Export library to support IBM XSL");
---
drivers/misc/cxl/cxllib.c | 13 +++--
features will be added soon:
- phb reset when switching to capi mode.
- cxllib update to support new functions.
Signed-off-by: Christophe Lombard
Acked-by: Frederic Barrat
---
Changelog[v3]
- Update commit message
Changelog[v2]
- Rebase to latest upstream.
- Update the function is_page_fault
dump these regs on PSL error interrupt thereby bringing the
behavior in line with PSL on POWER-8.
Signed-off-by: Vaibhav Jain
---
drivers/misc/cxl/native.c | 13 +++--
drivers/misc/cxl/pci.c| 1 +
2 files changed, 12 insertions(+), 2 deletions(-)
sounds good.
Acked-by: Chris
: Christophe Lombard
---
Changelog[v2]
- Rebase to latest upstream.
- Update the function is_page_fault()
---
drivers/misc/cxl/cxl.h | 2 ++
drivers/misc/cxl/fault.c | 15 ++-
drivers/misc/cxl/pci.c | 46 +++---
3 files changed, 27
Le 28/08/2017 à 06:15, Vaibhav Jain a écrit :
Make sure to set the valid-bit in software-state field of the
populated PE. This was earlier missing for dedicated mode AFUs, hence
was causing a PSL freeze when the AFU was activated.
Acked-by: Christophe Lombard
Signed-off-by: Vaibhav Jain
Le 24/08/2017 à 07:24, Andrew Donnellan a écrit :
On 24/08/17 00:58, Christophe Lombard wrote:
The PSL initialization sequence has been updated to DD2.
This patch adapts to the changes, retaining compatibility with DD1.
Tests performed on some of the new hardware.
If we're reta
Le 24/08/2017 à 09:09, Vaibhav Jain a écrit :
Hi Christophe,
Christophe Lombard writes:
+ /* For debugging with trace arrays */
+ /* Configure RX trace 0 segmented mode */
+ cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200ULL);
+ /* Configure RX trace 1
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