From: Hou Zhiqiang
The commit 0a121f9bc3f5 ("misc: pci_endpoint_test: Use streaming DMA
APIs for buffer allocation") changed to use streaming DMA APIs, however,
dma_map_single() might not return a 4KB aligned address, so add the
default_data as driver data for Layerscape PCIe controllers to make
From: Xiaowei Bao
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
drivers/misc/pci_endpoint_test.c
From: Xiaowei Bao
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++
1 file chang
From: Xiaowei Bao
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver
before, because the ls1046a platform don't support the MSIX feature
and msix_capable was always set to false.
Now that add the ls1088a platform with MSIX support, use the doorbell
method to support the MSIX featur
From: Xiaowei Bao
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Rob Herring
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality
From: Xiaowei Bao
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
Reviewed-by: Rob Herring
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch wit
From: Xiaowei Bao
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions
From: Xiaowei Bao
Each PF of EP device should have its own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and move the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
via a list.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase
From: Xiaowei Bao
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
Acked-by: Rob Herring
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 ++
1 file changed, 2 inserti
From: Xiaowei Bao
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqian
From: Xiaowei Bao
Add the doorbell mode of MSI-X in DWC EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
Signed-off-by: Hou Zhiqiang
---
V7:
- Rebase the patch without functionality change.
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
drivers/pci/con
From: Xiaowei Bao
Add multiple PFs support for DWC, due to different PF have different
config space, we use func_conf_select callback function to access
the different PF's config space, the different chip company need to
implement this callback function when use the DWC IP core and intend
to supp
From: Hou Zhiqiang
Add the PCIe EP multiple PF support for DWC and Layerscape, and use
a list to manage the PFs of each PCIe controller; add the doorbell
MSIX function for DWC; and refactor the Layerscape EP driver due to
some difference in Layercape platforms PCIe integration.
Hou Zhiqiang (1):
From: Hou Zhiqiang
LS1046a implements 3 PCIe 3.0 controllers.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 75 ++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
b/arch/arm64/boot/dts/fre
From: Hou Zhiqiang
Add PCIe controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
b/arch/arm64/boot/dts/f
From: Hou Zhiqiang
Signed-off-by: Hou Zhiqiang
---
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
drivers/pci/dwc/pci-layerscape.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b/Documenta
From: Hou Zhiqiang
Add MSI controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-ls1012a
From: Hou Zhiqiang
The ls1012a implement only 1 msi controller, and it is the same as
ls1043a.
Signed-off-by: Hou Zhiqiang
---
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
drivers/irqchip/irq-ls-scfg-msi.c| 1 +
2 files
From: Hou Zhiqiang
This patch set adds ls1012a MSI and PCIe support, including driver
and device tree nodes. The ls1046a's MSI support patch and PCIe
driver patch has been applied, so only adds the PCIe device tree
nodes.
Hou Zhiqiang (5):
irqchip/ls-scfg-msi: add LS1012a MSI support
arm64:
Hi David,
Thanks for your comments.
> -Original Message-
> From: David Laight [mailto:david.lai...@aculab.com]
> Sent: 2016年4月9日 0:01
> To: Zhiqiang Hou ; Scott Wood ;
> linuxppc-dev@lists.ozlabs.org; b...@kernel.crashing.org; pau...@samba.org;
> m...@ellerman.id.a
Hi Scott,
Thanks for your comments.
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: 2016年4月7日 6:01
> To: Zhiqiang Hou ; linuxppc-dev@lists.ozlabs.org;
> b...@kernel.crashing.org; pau...@samba.org; m...@ellerman.id.au
> Cc: Mingkai Hu
>
From: Hou Zhiqiang
Disable the subsector (4KiB) erase granularity to speed up the erase
operation.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/configs/85xx-hw.config | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/85xx-hw.config
b/arch/powerpc/configs/85xx-hw.config
From: Hou Zhiqiang
Starting with commit <8947e396a829> ("Documentation: dt: mtd:
replace "nor-jedec" binding with "jedec, spi-nor"") we have
"jedec,spi-nor" binding indicating support for JEDEC identification.
Use it for all flashes that are supposed to support READ ID op
according to the datash
Hi,
Any comments?
> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@freescale.com]
> Sent: 2016年1月4日 15:45
> To: linuxppc-dev@lists.ozlabs.org; b...@kernel.crashing.org; pau...@samba.org;
> m...@ellerman.id.au
> Cc: Scott Wood ; a...@linux-foundation.org;
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: 2016年1月27日 22:24
> To: Zhiqiang Hou ; Zhiqiang Hou
> ; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org; b...@kernel.crashing.org; pau...@samba.org;
> m...@ellerman.id.au; devic
Hi Herring and Kumar and Ian,
Can you help to apply this patch?
Thanks,
Zhiqiang
> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@nxp.com]
> Sent: 2015年12月22日 17:28
> To: Zhiqiang Hou ; linuxppc-dev@lists.ozlabs.org;
> Scott Wood ; ga...@kernel.cr
From: Hou Zhiqiang
Starting with commit <8947e396a829> ("Documentation: dt: mtd:
replace "nor-jedec" binding with "jedec, spi-nor"") we have
"jedec,spi-nor" binding indicating support for JEDEC identification.
Use it for all flashes that are supposed to support READ ID op
according to the datash
: Zhiqiang Hou
---
arch/powerpc/sysdev/fsl_pci.c | 24
1 file changed, 24 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index c69e88e..33e50f3 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -37,6
From: Hou Zhiqiang
On the t208xrdb and t1040rdb, the SPI devices is n25q512ax3
instead of n25q512a.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/t208xrdb.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arc
From: Hou Zhiqiang
Only the value PCIE_LTSSM_L0 stands for the link is up, instead
of >= PCIE_LTSSM_L0.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/sysdev/fsl_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.
Hi Rob,
Could you please take this patch into account?
Thanks,
Zhiqiang
> -Original Message-
> From: Zhiqiang Hou [mailto:zhiqiang@freescale.com]
> Sent: 2015年11月5日 11:16
> To: linuxppc-dev@lists.ozlabs.org; Scott Wood; ga...@kernel.crashing.org;
> b...@kernel.cr
Hi Scott,
Could you please help to apply this patch?
Thanks,
Zhiqiang
> -Original Message-
> From: Scott Wood
> Sent: 2015年11月20日 11:02
> To: Zhiqiang Hou; Zhiqiang Hou; linuxppc-dev@lists.ozlabs.org;
> ga...@kernel.crashing.org; b...@kernel.crashing.org; pau...
From: Harninder Rai
Signed-off-by: Harninder Rai
Signed-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
---
V4: V3:
- Remove gerrit stuff.
V2:
- Remove property clock-frequency.
arch/powerpc/boot/dts/bsc9132qds.dts | 15 ++
arch/powerpc/boot/dts/fsl/bsc9132si-post.dt
From: Harninder Rai
1. Use machine_arch_initcall to hook mpc85xx_common_publish_devices
This can ensure before pcibios_init() is called, pci controllers have
been probed and added to the hose_list.
2. Add a workaround for errata A-005434
For the BSC9132, PEX_PEXIWARn[TRGT] for all windows default
From: Harninder Rai
1. Use machine_arch_initcall to hook mpc85xx_common_publish_devices
This can ensure before pcibios_init() is called, pci controllers have
been probed and added to the hose_list.
2. Add a workaround for errata A-005434
For the BSC9132, PEX_PEXIWARn[TRGT] for all windows default
From: Harninder Rai
Signed-off-by: Harninder Rai
Signed-off-by: Minghuan Lian
Reviewed-by: Zang Tiefei-R61911
Reviewed-by: Kushwaha Prabhakar-B32579
Reviewed-by: Fleming Andrew-AFLEMING
Tested-by: Fleming Andrew-AFLEMING
Signed-off-by: Hou Zhiqiang
---
V3:
- Remove gerrit stuff.
V2:
- Re
From: Harninder Rai
Signed-off-by: Harninder Rai
Signed-off-by: Minghuan Lian
Change-Id: I4355add4a92d1fcf514843aea5ecadd2e2517969
Reviewed-on: http://git.am.freescale.net:8181/2454
Reviewed-by: Zang Tiefei-R61911
Reviewed-by: Kushwaha Prabhakar-B32579
Reviewed-by: Fleming Andrew-AFLEMING
Te
From: Harninder Rai
1. Use machine_arch_initcall to hook mpc85xx_common_publish_devices
This can ensure before pcibios_init() is called, pci controllers have
been probed and added to the hose_list.
2. Add a workaround for errata A-005434
For the BSC9132, PEX_PEXIWARn[TRGT] for all windows default
From: Harninder Rai
1. Use machine_arch_initcall to hook mpc85xx_common_publish_devices
This can ensure before pcibios_init() is called, pci controllers have
been probed and added to the hose_list.
2. Add a workaround for errata A-005434
For the BSC9132, PEX_PEXIWARn[TRGT] for all windows default
From: Harninder Rai
Signed-off-by: Harninder Rai
Signed-off-by: Minghuan Lian
Change-Id: I4355add4a92d1fcf514843aea5ecadd2e2517969
Reviewed-on: http://git.am.freescale.net:8181/2454
Reviewed-by: Zang Tiefei-R61911
Reviewed-by: Kushwaha Prabhakar-B32579
Reviewed-by: Fleming Andrew-AFLEMING
Te
From: Hou Zhiqiang
The c293pcie board is an endpoint device and it doesn't need PM,
so remove hooks pcibios_fixup_phb and pcibios_fixup_bus.
Signed-off-by: Hou Zhiqiang
---
Test on c293pcie board:
V2:
Rename the title of this patch.
Remove pcibios_fixup_bus that isn't used in EP.
arch
From: Hou Zhiqiang
Impact board list:
P1020MBG-PC. P1022DS, P2020RDB
All above boards have its PCIE memory range less than 0xbfff_,
but in dts its boundary value was 0xe000. Both of them was maped
to the same boundary 0xe000 which was Overlapped and crossed. Cpu
will access the illici
From: Hou Zhiqiang
The c293pcie board is an endpoint device, and it does't need PM.
Signed-off-by: Hou Zhiqiang
---
arch/powerpc/platforms/85xx/c293pcie.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/platforms/85xx/c293pcie.c
b/arch/powerpc/platforms/85xx/c293pcie.c
index 8
43 matches
Mail list logo
