On 4/30/2014 1:45 AM, Michael Ellerman wrote:
>> > Are 40x considered booke?
> You tell me.
>
The original 401, 403 and 405 cores predate the actual existence of what we now
call Book E.
But they most certainly contained features that would eventually become Book E
(different timers,
software
On 2/6/2014 12:08 PM, Peter Zijlstra wrote:
>>> Can you pair lwarx with sthcx ? I couldn't immediately find the answer
>>> > > in the PowerISA doc. If so I think you can do better by being able to
>>> > > atomically load both tickets but only storing the head without affecting
>>> > > the tail.
>>
On 12/12/2013 9:08 AM, Tom Musta wrote:
> On 12/10/2013 10:57 PM, Paul Mackerras wrote:
>> On Wed, Dec 11, 2013 at 02:54:40PM +1100, Paul Mackerras wrote:
>
>>> This breaks 32-bit big-endian (as well as making the code longer and
>>> more complex).
>>
>&
On 12/10/2013 10:57 PM, Paul Mackerras wrote:
> On Wed, Dec 11, 2013 at 02:54:40PM +1100, Paul Mackerras wrote:
>> This breaks 32-bit big-endian (as well as making the code longer and
>> more complex).
>
> And in fact none of this code will get executed in little-endian mode
> anyway, since we st
On 12/2/2013 3:10 AM, Philippe Bergheaud wrote:
> This patch fixes the disassembler of the powerpc kernel debugger xmon,
> for little-endian.
>
> Signed-off-by: Philippe Bergheaud
> ---
> arch/powerpc/xmon/xmon.c |4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/xmon/
On 11/3/2013 8:34 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-10-31 at 13:38 -0500, Tom wrote:
>> From: Tom Musta
>>
>> This patch addresses unaligned single precision floating point loads
>> and stores in the single-step code. The old implementation
>
On 10/30/2013 2:43 PM, Geert Uytterhoeven wrote:
On Wed, Oct 30, 2013 at 8:35 PM, Tom Musta wrote:
On 10/30/2013 12:43 PM, Andreas Schwab wrote:
Tom Musta writes:
+#ifdef __LITTLE_ENDIAN__
+ if (!regs->msr & MSR_LE)
That won't work.
Andreas.
Please elaborate.
On 10/30/2013 12:43 PM, Andreas Schwab wrote:
Tom Musta writes:
+#ifdef __LITTLE_ENDIAN__
+ if (!regs->msr & MSR_LE)
That won't work.
Andreas.
Please elaborate.
___
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Linuxppc-dev@lists.ozla
This patch addresses unaligned single precision floating point loads
and stores in the single-step code. The old implementation
improperly treated an 8 byte structure as an array of two 4 byte
words, which is a classic little endian bug.
Signed-off-by: Tom Musta
---
arch/powerpc/lib/sstep.c
reversal operation.
Signed-off-by: Tom Musta
---
arch/powerpc/lib/sstep.c | 45 +
1 files changed, 45 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 5e0d0e9..570f2af 100644
--- a/arch/powerpc/lib
a kernel compiled for BE and vice verse).
Signed-off-by: Tom Musta
---
arch/powerpc/lib/sstep.c | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index b1faa15..5e0d0e9 100644
--- a/arch/powerpc/lib/sstep.c
general problem with unaligned little endian loads and stores.
This is addressed by the second patch.
Finally, there is a problem with unaligned single precision floating point
loads and stores which is addressed by the third patch.
Tom Musta (3):
powerpc: Enable emulate_step In Little Endian Mode
This patch enables alignment handling for the load/store floating point
pair instructions (lfdp, lfdpx, stfdp, stfdpx). The handler routine
is properly coded and only needs to be enabled.
Signed-off-by: Tom Musta
---
arch/powerpc/kernel/align.c |6 --
1 files changed, 0 insertions
byte swapping flag for the string instructions
in little endian builds. This effectively disables the byte swapping
logic.
Signed-off-by: Tom Musta
---
arch/powerpc/kernel/align.c | 21 -
1 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel
This patch series fixes two bugs in the PowerPC Little Endian alignment
handler.
Tom Musta (2):
powerpc: Fix Handler of Unaligned Load/Store Strings
powerpc: Enable Little Endian Alignment Handler for Float Pair
Instructions
arch/powerpc/kernel/align.c | 25
On 10/3/2013 2:03 PM, Sukadev Bhattiprolu wrote:
Michael Ellerman [mich...@ellerman.id.au] wrote:
|
| if (lower == 6)
| if (upper <= 1)
| return true;
| return false;
v
Note that this case covers the lvsl/lvsr instructions, which, despite their
On 9/13/2013 7:49 PM, Sukadev Bhattiprolu wrote:
Implement is_instr_load_store() to detect whether a given instruction
is one of the fixed-point or floating-point load/store instructions.
This function will be used in a follow-on patch to save memory hierarchy
information of the load/store.
+/*
> > Isn't that code occasionally used with uprobes too nowadays ?
>
> Yes. I believe so.
I'm going to back-pedal a little. I reread code and can connect
single step code to kprobes but not necessarily to uprobes. So
I am not sure that this code is used with uprobes.
mangled.
I will find a better setup and resubmit.
> Isn't that code occasionally used with uprobes too nowadays ?
Yes. I believe so.
Tom Musta (tmu...@us.ibm.com)
Senior Software Engineer
Blue Gene Kernel Development
IBM Rochester
(507) 253-4
To: linuxppc-dev@lists.ozlabs.org
Subject: [PATCH] powerpc: OE=1 Form Instructions Not Decoded Correctly
From: Tom Musta
PowerISA uses instruction bit 21 to indicate that the overflow (OV) bit
of the XER is to be set, as well as its corresponding sticky bit (SO).
This patch addresses two defects
To: linuxppc-dev@lists.ozlabs.org
Subject: [PATCH] powerpc: Unaligned stores and stmw are broken in PowerISA
emulation code
From: Tom Musta
The stmw instruction was incorrectly decoded as an update form instruction
and thus the RA
register was being clobbered.
Also, the utility routine to
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