Hi Russell,
On Mon, 2021-11-01 at 19:20 +1000, Russell Currey wrote:
> On Sun, 2021-10-31 at 22:43 -0400, Joe Lawrence wrote:
> > Starting with 5.14 kernels, I can reliably reproduce a crash [1] on
> > ppc64le when loading livepatches containing late klp-relocations
> > [2].
> > These are relocati
On Fri, 2019-08-09 at 14:11 +0530, Bharata B Rao wrote:
> KVMPPC driver to manage page transitions of secure guest
> via H_SVM_PAGE_IN and H_SVM_PAGE_OUT hcalls.
>
> H_SVM_PAGE_IN: Move the content of a normal page to secure page
> H_SVM_PAGE_OUT: Move the content of a secure page to normal page
>
On Sat, 2019-07-13 at 13:47 +1000, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
> > The performance monitoring unit (PMU) registers are saved on guest
> > exit
> > when the guest has set the pmcregs_in_use flag in its lppaca, if it
> > exists, or uncondit
On Fri, 2019-07-12 at 23:09 +1000, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
> > The virtual real mode addressing (VRMA) mechanism is used when a
> > partition is using HPT (Hash Page Table) translation and performs
> > real mode accesses (MSR[IR|DR] = 0) in no
consequences.
To avoid this outcome have the guest explicitly limit the size of the
RMA to the current maximum, which is 1TB. This means that even if the
first memory block is larger than 1TB, only the first 1TB should be
accessed in real mode.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc
"KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index b682a429f
of running it's own guests (CONFIG_KVM_BOOK3S_HV_POSSIBLE).
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/pmc.h | 5 ++---
1 file changed, 2 insertions(+), 3 dele
guest with "-machine pseries,cap-nested-hv=false"
on the qemu commandline.
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv.c | 2 ++
1 file changed, 2 ins
"KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index d3684509da35.
will return control to L1 when this
goes negative by delivering an H_DECREMENTER exception.
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on
P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv.c | 11 +--
the erat invalidation.
Fixes: 70ea13f6e609 "KVM: PPC: Book3S HV: Flush TLB on secondary radix threads"
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv_builtin.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c
b/arch/p
On Mon, 2019-06-17 at 11:06 +0200, Cédric Le Goater wrote:
> On 17/06/2019 09:16, Suraj Jitindar Singh wrote:
> > Series contains 2 patches to fix the host in kernel handling of the
> > hcall
> > h_set_dawr.
> >
> > First patch from Michael Neuling is just a
to do this for
it when it calls H_ENTER_NESTED.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 70
From: Michael Neuling
Commit c1fe190c0672 ("powerpc: Add force enable of DAWR on P9
option") screwed up some assembler and corrupted a pointer in
r3. This resulted in crashes like the below:
[ 44.374746] BUG: Kernel NULL pointer dereference at 0x13bf
[ 44.374848] Faulting instruction
Series contains 2 patches to fix the host in kernel handling of the hcall
h_set_dawr.
First patch from Michael Neuling is just a resend added here for clarity.
Michael Neuling (1):
KVM: PPC: Book3S HV: Fix r3 corruption in h_set_dabr()
Suraj Jitindar Singh (1):
KVM: PPC: Book3S HV: Only
On Thu, 2019-06-13 at 10:16 +1000, Michael Neuling wrote:
> On Wed, 2019-06-12 at 09:43 +0200, Cédric Le Goater wrote:
> > On 12/06/2019 09:22, Michael Neuling wrote:
> > > In commit c1fe190c0672 ("powerpc: Add force enable of DAWR on P9
> > > option") I screwed up some assembler and corrupted a po
On Wed, 2019-03-27 at 17:51 +0100, Cédric Le Goater wrote:
> On 3/27/19 5:37 PM, Cédric Le Goater wrote:
> > On 3/27/19 1:36 PM, Sebastian Andrzej Siewior wrote:
> > > With qemu-system-ppc64le -machine pseries -smp 4 I get:
> > >
> > > > # chrt 1 hackbench
> > > > Running in process mode with 10
n order to achieve the same result, add a barrier_nospec to the
raw_copy_in_user() function before loading from such a user-controlled
pointer.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/uaccess.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/ua
Add KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST &
KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE to the characteristics returned from
the H_GET_CPU_CHARACTERISTICS H-CALL, as queried from either the
hypervisor or the device tree.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/uapi/asm/kvm.h
This adds an entry to the kvm_stats_debugfs directory which provides the
number of large (2M or 1G) pages which have been used to setup the guest
mappings.
Signed-off-by: Suraj Jitindar Singh
---
V1 -> V2:
- Rename debugfs files from num_[2M/1G]_pages to largepages_[2M/1G] to match
x86
a
This adds an entry to the kvm_stats_debugfs directory which provides the
number of large (2M or 1G) pages which have been used to setup the guest
mappings.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_host.h| 2 ++
arch/powerpc/kvm/book3s.c | 3
return without needing to load
the instruction from guest memory.
For now we restrict this to stores as this is the only use case at
present.
For a normal guest the effect is negligible, however for a nested guest
we save on the order of 5us per access.
Signed-off-by: Suraj Jitindar Singh
---
arch
n now be allowed.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 9 -
arch/powerpc/kvm/book3s_hv_nested.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c
b/arch/powerp
implementation for the kvm-hv module.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kvm/book3s_64_mmu_radix.c | 7 ++--
arch/powerpc/kvm/book3s_hv.c | 6 ++-
arch/powerpc/kvm
an L1 guest emulate a device for an L2
guest which is then passed through to an L3 guest.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 2 +-
arch/powerpc/include/asm/kvm_host.h | 3 +++
arch/powerpc/kvm/book3s_hv.c | 12 ++
arch/powerp
rying the access.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 95859c53a5cd..cb029fcab404 100644
--- a/arch/powerpc/kvm/powe
using the radix
mmu then we can call the functions to access quadrant 1 and 2.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_ppc.h | 4
arch/powerpc/kvm/book3s_hv.c | 40 ++
2 files changed, 44 insertions(+)
diff --git a/arch
rants aren't defined
for the hash mmu.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kernel/exceptions-64s.S | 9
arch/powerpc/kvm/book3s_64_mmu_radix.c | 97 ++
arch/powerpc/mm/fault.c
for if the vcpu is running a nested guest.
Currently all nested guests must be radix but this may change in the
future.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s_64.h | 13 +
arch/powerpc/kvm/book3s_hv_nested.c | 1 +
2 files changed, 14
CPU_FTR_HVMODE.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2869a299c4ed..95859c53a5cd 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc
platforms
7/8: None
8/8: None
Suraj Jitindar Singh (8):
KVM: PPC: Only report KVM_CAP_SPAPR_TCE_VFIO on powernv machines
KVM: PPC: Book3S HV: Add function kvmhv_vcpu_is_radix()
KVM: PPC: Book3S HV: Implement functions to access quadrants 1 & 2
KVM: PPC: Add load_from_eaddr and store
n now be allowed.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 9 -
arch/powerpc/kvm/book3s_hv_nested.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c
b/arch/powerp
implementation for the kvm-hv module.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kvm/book3s_64_mmu_radix.c | 7 ++--
arch/powerpc/kvm/book3s_hv.c | 6 ++-
arch/powerpc/kvm
an L1 guest emulate a device for an L2
guest which is then passed through to an L3 guest.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 2 +-
arch/powerpc/include/asm/kvm_host.h | 3 +++
arch/powerpc/kvm/book3s_hv.c | 12 ++
arch/powerp
rying the access.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 95859c53a5cd..cb029fcab404 100644
--- a/arch/powerpc/kvm/powe
using the radix
mmu then we can call the functions to access quadrant 1 and 2.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_ppc.h | 4
arch/powerpc/kvm/book3s_hv.c | 40 ++
2 files changed, 44 insertions(+)
diff --git a/arch
rants aren't defined
for the hash mmu.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kernel/exceptions-64s.S | 9
arch/powerpc/kvm/book3s_64_mmu_radix.c | 97 ++
arch/powerpc/mm/fault.c
for if the vcpu is running a nested guest.
Currently all nested guests must be radix but this may change in the
future.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s_64.h | 13 +
arch/powerpc/kvm/book3s_hv_nested.c | 1 +
2 files changed, 14
CPU_FTR_HVMODE.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2869a299c4ed..95859c53a5cd 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc
for the args in H_COPY_TOFROM_GUEST to
match the comment.
8/8: None
Suraj Jitindar Singh (8):
KVM: PPC: Only report KVM_CAP_SPAPR_TCE_VFIO on powernv machines
KVM: PPC: Book3S HV: Add function kvmhv_vcpu_is_radix()
KVM: PPC: Book3S HV: Implement functions to access quadrants 1 & 2
On Thu, 2018-12-13 at 16:24 +1100, Paul Mackerras wrote:
> On Mon, Dec 10, 2018 at 02:58:24PM +1100, Suraj Jitindar Singh wrote:
> > A guest cannot access quadrants 1 or 2 as this would result in an
> > exception. Thus introduce the hcall H_COPY_TOFROM_GUEST to be used
> > b
n now be allowed.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 9 -
arch/powerpc/kvm/book3s_hv_nested.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c
b/arch/powerp
implementation for the kvm-hv module.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kvm/book3s_64_mmu_radix.c | 7 ++--
arch/powerpc/kvm/book3s_hv.c | 6 ++-
arch/powerpc/kvm
an L1 guest emulate a device for an L2
guest which is then passed through to an L3 guest.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 2 +-
arch/powerpc/include/asm/kvm_host.h | 3 +++
arch/powerpc/kvm/book3s_hv.c | 12 ++
arch/powerp
rying the access.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 95859c53a5cd..cb029fcab404 100644
--- a/arch/powerpc/kvm/powe
using the radix
mmu then we can call the functions to access quadrant 1 and 2.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_ppc.h | 4
arch/powerpc/kvm/book3s_hv.c | 40 ++
2 files changed, 44 insertions(+)
diff --git a/arch
rants aren't defined
for the hash mmu.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kernel/exceptions-64s.S | 9
arch/powerpc/kvm/book3s_64_mmu_radix.c | 97 ++
arch/powerpc/mm/fault.c
for if the vcpu is running a nested guest.
Currently all nested guests must be radix but this may change in the
future.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s_64.h | 13 +
arch/powerpc/kvm/book3s_hv_nested.c | 1 +
2 files changed, 14
CPU_FTR_HVMODE.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2869a299c4ed..95859c53a5cd 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc
endianess in kvmppc_complete_mmio_load()
7/8: None
8/8: None
Suraj Jitindar Singh (8):
KVM: PPC: Only report KVM_CAP_SPAPR_TCE_VFIO on powernv machines
KVM: PPC: Book3S HV: Add function kvmhv_vcpu_is_radix()
KVM: PPC: Book3S HV: Implement functions to access quadrants 1 & 2
KVM: PPC: Add loa
On Fri, 2018-12-07 at 14:43 +1100, Suraj Jitindar Singh wrote:
> This patch series allows for emulated devices to be passed through to
> nested
> guests, irrespective of at which level the device is being emulated.
>
> Note that the emulated device must be using dma, not virtio.
&
n now be allowed.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 9 -
arch/powerpc/kvm/book3s_hv_nested.c| 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c
b/arch/powerp
implementation for the kvm-hv module.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kvm/book3s_64_mmu_radix.c | 7 ++--
arch/powerpc/kvm/book3s_hv.c | 6 ++-
arch/powerpc/kvm
an L1 guest emulate a device for an L2
guest which is then passed through to an L3 guest.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 2 +-
arch/powerpc/include/asm/kvm_host.h | 3 +++
arch/powerpc/kvm/book3s_hv.c | 12 ++
arch/powerp
rying the access.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 95859c53a5cd..cb029fcab404 100644
--- a/arch/powerpc/kvm/powe
using the radix
mmu then we can call the functions to access quadrant 1 and 2.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_ppc.h | 4
arch/powerpc/kvm/book3s_hv.c | 40 ++
2 files changed, 44 insertions(+)
diff --git a/arch
since quadrants aren't defined
for the hash mmu.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s.h | 4 ++
arch/powerpc/kernel/exceptions-64s.S | 9
arch/powerpc/kvm/book3s_64_mmu_radix.c | 97 ++
arch/powerpc/mm/fault.c
for if the vcpu is running a nested guest.
Currently all nested guests must be radix but this may change in the
future.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/kvm_book3s_64.h | 13 +
arch/powerpc/kvm/book3s_hv_nested.c | 1 +
2 files changed, 14
CPU_FTR_HVMODE.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/powerpc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2869a299c4ed..95859c53a5cd 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc
ecause we don't set
the BOOK3S_HFLAG_MULTI_PGSIZE flag in the hflags in kvmppc_set_pvr_pr()
on POWER9.
POWER9 does indeed have support for 1T segments, so add a case for
POWER9 to the switch statement to ensure it is set.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm/book3s_pr.c |
qemu-system-ppc64 -device vfio-pci,host=:00:00.0
4. L(n+2) can now access the device which will be emulated at L(n)
Suraj Jitindar Singh (8):
KVM: PPC: Only report KVM_CAP_SPAPR_TCE_VFIO on powernv machines
KVM: PPC: Book3S HV: Add function kvmhv_vcpu_is_radix()
KVM: PPC: Boo
On Sun, 2018-12-02 at 21:52 +0100, Thomas Meyer wrote:
> NULL check before some freeing functions is not needed.
Technically true, however I think a comment should be added then to
make it clearer to someone reading the code why this is ok.
See below.
Suraj.
>
> Signed-off-by: Thomas Meyer
>
c1b0 SPRG2
> 772f9565a280 SPRG3
> SPRG4 SPRG5 SPRG6
> 0000 SPRG7 0000
> HSRR0 HSRR1
>CFAR 0000
> LPCR 03d40413
>PTCR
5
bytes 23-26 of the ibm,architecture.vec node. Each of these options
is a pair of bytes, thus for 4 options we have a max length of 8 bytes.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kernel/prom_init.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powe
ff-by: Suraj Jitindar Singh
---
arch/powerpc/platforms/pseries/lparcfg.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/lparcfg.c
b/arch/powerpc/platforms/pseries/lparcfg.c
index 7c872dc01bdb..8bd590af488a 100644
--- a/arch/powerpc/plat
This patch series removes two Variable Length Arrays (VLAs) from
the powerpc code.
Series based on v4.19-rc2
Suraj Jitindar Singh (2):
powerpc/prom: Remove VLA in prom_check_platform_support()
powerpc/pseries: Remove VLA from lparcfg_write()
arch/powerpc/kernel/prom_init.c | 7
On Tue, 2018-01-09 at 23:44 +1100, Alexey Kardashevskiy wrote:
> On 09/01/18 19:39, Suraj Jitindar Singh wrote:
> > On Tue, 2018-01-09 at 15:48 +1100, Paul Mackerras wrote:
> > > This adds three new capabilities that give userspace information
> > > about
> > &g
s as a speculation barrier.
>
> KVM_CAP_PPC_SAFE_INDIRECT_BRANCH reports the vulnerability of the
> machine to attacks based on poisoning the indirect branch predictor.
> No workaround that requires software changes is provided; the current
> hardware fix is to prevent speculation p
On Tue, 2018-01-09 at 15:48 +1100, Paul Mackerras wrote:
> This adds three new capabilities that give userspace information
> about
> the underlying machine's level of vulnerability to the Meltdown and
> Spectre attacks, and what instructions the hardware implements to
> assist software to work aro
On Tue, 2018-01-09 at 15:48 +1100, Paul Mackerras wrote:
> This adds three new capabilities that give userspace information
> about
> the underlying machine's level of vulnerability to the Meltdown and
> Spectre attacks, and what instructions the hardware implements to
> assist software to work aro
On Fri, 2017-12-08 at 17:11 +1100, Paul Mackerras wrote:
> POWER9 has hardware bugs relating to transactional memory and thread
> reconfiguration (changes to hardware SMT mode). Specifically, the
> core
> does not have enough storage to store a complete checkpoint of all
> the
> architected state
On Wed, 2017-08-09 at 20:30 +1000, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
>
> > The host process table base is stored in the partition table by
> > calling
> > the function native_register_process_table(). Currently this just
> > sets
> >
On Fri, 2017-08-04 at 11:31 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2017-08-04 at 11:02 +1000, Suraj Jitindar Singh wrote:
> >
> > I guess there's the possibility of:
> > [x] randomly crash
> >
> > This is required to run a powernv kernel as a gues
On Thu, 2017-08-03 at 17:35 +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2017-08-03 at 16:30 +1000, Michael Ellerman wrote:
> > Suraj Jitindar Singh writes:
> >
> > > The host process table base is stored in the partition table by
> > > calling
> > >
to call
mmu_partition_table_set_entry(), this ensures all appropriate
invalidation will be performed.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/mm/pgtable-radix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm
& cpu_to_be64(_PAGE_DEVMAP));
> + uint64_t mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
> +
> + return (pte_raw(pte) & mask) == mask;
> }
>
> static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
Reviewed-by: Suraj Jitindar Singh
On Thu, 2017-07-27 at 13:14 +1000, Michael Ellerman wrote:
> jos...@linux.vnet.ibm.com writes:
> > On Thu, Jul 20, 2017 at 10:18:18PM -0300, jos...@linux.vnet.ibm.com
> > wrote:
> > > On Thu, Jul 20, 2017 at 03:21:59PM +1000, Paul Mackerras wrote:
> > > >
> > > > Did you check the host kernel log
e PR KVM
> is not supported on POWER9 yet.
>
> This is partly based on an earlier patch by Oliver O'Halloran.
>
> Signed-off-by: Paul Mackerras
Tested with a hacked up qemu and upstream guest/host (with these
patches).
Tested-by: Suraj Jitindar Singh
> ---
> arch/powerpc
,architecture-vec-5 property of the
chosen node to check whether we should run as hash or radix.
ibm,arch-vec-5-platform-support format:
index value pairs: ...
index: Option vector 5 byte number
val: Some representation of supported values
Signed-off-by: Suraj Jitindar Singh
---
V2 ->
ix" on the command line. The next patch will add support for
the new CAS format, thus we need to parse the command line before calling
CAS so we can correctly select which mmu we would like to use.
Signed-off-by: Suraj Jitindar Singh
Reviewed-by: Paul Mackerras
---
V1 -> V3:
- Reword commit m
On Fri, 2017-02-24 at 15:28 +1100, Matt Brown wrote:
> The HDAT data area is consumed by skiboot and turned into a device-
> tree.
> In some cases we would like to look directly at the HDAT, so this
> patch
> adds a sysfs node to allow it to be viewed. This is not possible
> through
> /dev/mem as
,architecture-vec-5 property of the
chosen node to check whether we should run as hash or radix.
ibm,arch-vec-5-platform-support format:
index value pairs: ...
index: Option vector 5 byte number
val: Some representation of supported values
Signed-off-by: Suraj Jitindar Singh
---
V1 ->
ix" on the command line. The next patch will add support for
the new CAS format, thus we need to parse the command line before calling
CAS so we can correctly select which mmu we would like to use.
Signed-off-by: Suraj Jitindar Singh
Reviewed-by: Paul Mackerras
---
V1 -> V2:
- Reword commit m
On Thu, 2017-02-23 at 15:44 +1100, Paul Mackerras wrote:
> On Tue, Feb 21, 2017 at 05:06:11PM +1100, Suraj Jitindar Singh wrote:
> >
> > The CAS process has been updated to change how the host to guest
> Once again, explain CAS; perhaps "The ibm,client-architecture-supp
whether we should run as hash or radix.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/prom.h | 16 ---
arch/powerpc/kernel/prom_init.c | 99 +++--
arch/powerpc/mm/init_64.c | 31 ++---
3 files changed, 130 insertions(+), 16
so we can correctly represent which mmu we would like to use.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kernel/prom_init.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index d3db1b
On Fri, 2017-02-17 at 10:59 +1100, Russell Currey wrote:
> Signed-off-by: Russell Currey
Tested-in-QEMU-by: Suraj Jitindar Singh
> ---
> arch/powerpc/kernel/cputable.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/powerpc/kernel/cputable.
it hpte_init_pseries(void)
> mmu_hash_ops.flush_hash_range =
> pSeries_lpar_flush_hash_range;
> mmu_hash_ops.hpte_clear_all = pseries_hpte_clear_all;
> mmu_hash_ops.hugepage_invalidate =
> pSeries_lpar_hugepage_invalidate;
> + register_process_table =
> pseries_lpar_register_process_table;
> }
>
> void radix_init_pseries(void)
FWIW:
Reviewed-by: Suraj Jitindar Singh
On Thu, 2017-01-12 at 20:07 +1100, Paul Mackerras wrote:
> This adds a few last pieces of the support for radix guests:
>
> * Implement the backends for the KVM_PPC_CONFIGURE_V3_MMU and
> KVM_PPC_GET_RMMU_INFO ioctls for radix guests
>
> * On POWER9, allow secondary threads to be on/off-lined w
On Thu, 2017-01-12 at 20:07 +1100, Paul Mackerras wrote:
> This adapts our implementations of the MMU notifier callbacks
> (unmap_hva, unmap_hva_range, age_hva, test_age_hva, set_spte_hva)
> to call radix functions when the guest is using radix. These
> implementations are much simpler than for HP
On Thu, 2017-01-12 at 20:07 +1100, Paul Mackerras wrote:
> This adds the code to construct the second-level ("partition-scoped"
> in
> architecturese) page tables for guests using the radix MMU. Apart
> from
> the PGD level, which is allocated when the guest is created, the rest
> of the tree is a
On Thu, 2017-01-12 at 20:07 +1100, Paul Mackerras wrote:
> This adds the implementation of the KVM_PPC_CONFIGURE_V3_MMU ioctl
> for HPT guests on POWER9. With this, we can return 1 for the
> KVM_CAP_PPC_MMU_HASH_V3 capability.
>
> Signed-off-by: Paul Mackerras
> ---
> arch/powerpc/include/asm/k
On Tue, 2016-12-20 at 22:40 +1100, Paul Mackerras wrote:
> Currently, if the kernel is running on a POWER9 processor under a
> hypervisor, it will try to use the radix MMU even though it doesn't
> have the necessary code to use radix under a hypervisor (it doesn't
> negotiate use of radix, and it d
the PCR.
We also add a check to ensure the processor we are running on is capable of
emulating the chosen processor (for example a POWER7 cannot emulate a
POWER8, similarly with a POWER8 and a POWER9).
Based on work by: Paul Mackerras
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm
moment) we need a
PCR_ARCH_300 bit to represent this, however currently there is no such bit
defined by the ISA. Thus we define a 'dummy' v3.00 compat bit to be used.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/reg.h | 11 +++
1 file changed, 11 insertion
nge
V2 -> V3:
- Reworked logic again, no functional change
V3 -> V4:
- Added a comment in the first patch to clarify why a 'dummy' PCR v3.00
value is needed
Suraj Jitindar Singh (2):
powerpc: Define new ISA v3.00 logical PVR value and PCR register value
powerpc/kvm: Update kvm
On Thu, 2016-11-10 at 21:36 +1100, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
>
> >
> > On Tue, 2016-11-08 at 19:21 +1100, Michael Ellerman wrote:
> > >
> > > Suraj Jitindar Singh writes:
> > >
> > > >
> > > &
than 24
and 23.
Fixes: 2bfd65e45e877fb5704730244da67c748d28a1b8
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/mm/pgtable-radix.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index ed7bddc..80f3479
On Tue, 2016-11-08 at 19:21 +1100, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
>
> >
> > ISA 3.00 adds the logical PVR value 0x0f05, so add a definition
> > for
> > this.
> >
> > Define PCR_ARCH_207 to reflect ISA 2.07 compatibility m
the PCR.
We also add a check to ensure the processor we are running on is capable of
emulating the chosen processor (for example a POWER7 cannot emulate a
POWER8, similarly with a POWER8 and a POWER9).
Based on work by: Paul Mackerras
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/kvm
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