o
> side effects, making them eligible for compiler optimization.
>
> Build tested ARCH=openrisc defconfig with GCC or1k-linux 15.1.0.
THis looks ok to me.
> Link: https://github.com/KSPP/linux/issues/364 [1]
> Signed-off-by: Kees Cook
Acked-by: Stafford Horne
> ---
> arch
ex 44fc1fd56717..7925ce09ab5a 100644
> --- a/arch/openrisc/include/asm/page.h
> +++ b/arch/openrisc/include/asm/page.h
> @@ -18,7 +18,7 @@
>
> /* PAGE_SHIFT determines the page size */
>
> -#define PAGE_SHIFT 13
> +#define PAGE_SHIFT CONFIG_PAGE_SHIFT
> #ifdef __ASSEMBLY__
> #define PAGE_SIZE (1 << PAGE_SHIFT)
> #else
For the openrisc bits,
Acked-by: Stafford Horne
((pfn) < max_mapnr)
> -
> #define virt_addr_valid(kaddr) (pfn_valid(virt_to_pfn(kaddr)))
>
> #endif /* __ASSEMBLY__ */
For OpenRISC
Acked-by: Stafford Horne
ow_registers(regs);
> }
>
> -void release_thread(struct task_struct *dead_task)
> -{
> -}
> -
> /*
> * Copy the thread-specific (arch specific) info from the current
> * process to the new one p
For OpenRISC bits.
Acked-by: Stafford Horne
On Fri, Jul 22, 2022 at 06:38:21PM -0500, Bjorn Helgaas wrote:
> On Sat, Jul 23, 2022 at 06:49:41AM +0900, Stafford Horne wrote:
> > The definition of the pci header function pci_get_legacy_ide_irq is only
> > used in platforms that support PNP. So many of the architecutres
devices supported on x86_32 ever set this. A new global
header linux/isa-dma.h is added to provide a common place to maintain
the definition.
Suggested-by: Arnd Bergmann
Suggested-by: Christoph Hellwig
Acked-by: Geert Uytterhoeven
Reviewed-by: Christoph Hellwig
Signed-off-by: Stafford Horne
: Rafael J. Wysocki
Reviewed-by: Christoph Hellwig
Co-developed-by: Arnd Bergmann
Signed-off-by: Arnd Bergmann
Signed-off-by: Stafford Horne
---
arch/alpha/include/asm/pci.h | 6 --
arch/arm/include/asm/pci.h | 5 -
arch/arm64/include/asm/pci.h | 6 --
arch/csky/include
: Rafael J. Wysocki
Reviewed-by: Christoph Hellwig
Co-developed-by: Arnd Bergmann
Signed-off-by: Arnd Bergmann
Signed-off-by: Stafford Horne
---
Since v4:
- Also remove pci_get_legacy_ide_irq from arm64, csky, riscv at this point.
arch/alpha/include/asm/pci.h | 6 --
arch/arm/include
devices supported on x86_32 ever set this. A new global
header linux/isa-dma.h is added to provide a common place to maintain
the definition.
Suggested-by: Arnd Bergmann
Suggested-by: Christoph Hellwig
Signed-off-by: Stafford Horne
---
Since v3:
- New patch.
arch/alpha/include/asm/dma.h
-developed-by: Arnd Bergmann
Signed-off-by: Stafford Horne
---
Since v3:
- Further remove the definictions of pci_get_legacy_ide_irq from x86 and use
the libata macros.
- Add Acked-bys.
arch/alpha/include/asm/pci.h | 6 --
arch/arm/include/asm/pci.h | 5 -
arch/arm64/include/asm
, openrisc, etc.
The existing code in pci.h is moved out to x86. On other architectures
we clean up any outstanding references.
Suggested-by: Arnd Bergmann
Link:
https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn=Jbvf=nkbpvazcycyv40pzncj...@mail.gmail.com/
Signed-off-by: Stafford Horne
On Sun, Jul 17, 2022, 6:23 PM Geert Uytterhoeven
wrote:
> Hi Stafford,
>
> On Sun, Jul 17, 2022 at 5:35 AM Stafford Horne wrote:
> > The generic pci.h header now only provides a definition of
> > pci_get_legacy_ide_irq which is used by architectures that support PNP.
>
, openrisc, etc.
The existing code in pci.h is moved out to x86. On other architectures
we clean up any outstanding references.
Suggested-by: Arnd Bergmann
Link:
https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn=Jbvf=nkbpvazcycyv40pzncj...@mail.gmail.com/
Signed-off-by: Stafford Horne
On Thu, Jul 14, 2022 at 06:45:27PM -0700, Max Filippov wrote:
> On Thu, Jul 14, 2022 at 2:47 PM Stafford Horne wrote:
> >
> > The generic pci.h header provides a definition of pci_get_legacy_ide_irq
> > which is used by architectures that use PC-style interrupt numbers.
>
to architectures.
Suggested-by: Arnd Bergmann
Link:
https://lore.kernel.org/lkml/CAK8P3a0JmPeczfmMBE__vn=Jbvf=nkbpvazcycyv40pzncj...@mail.gmail.com/
Signed-off-by: Stafford Horne
---
arch/alpha/include/asm/pci.h | 1 -
arch/ia64/include/asm/pci.h| 1 -
arch/m68k/include/asm/pci.h| 7
AGE_READONLY_X,
> + [VM_SHARED | VM_WRITE] = PAGE_SHARED,
> + [VM_SHARED | VM_WRITE | VM_READ]= PAGE_SHARED_X,
> + [VM_SHARED | VM_EXEC] = PAGE_READONLY,
> + [VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_X,
> + [VM_SHARED | VM_EXEC | VM_WRITE]= PAGE_SHARED,
> + [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_X
> +};
> +DECLARE_VM_GET_PAGE_PROT
Looks good.
Acked-by: Stafford Horne
onas Bonn
> Cc: openr...@lists.librecores.org
> Cc: linux-ker...@vger.kernel.org
> Acked-by: Stafford Horne
> Signed-off-by: Anshuman Khandual
Is it possible to retract my Acked-by? I was following the discussion of this
new function actually being sub optimal. So as far
long count)
> {
> - mm_segment_t old_fs;
> long ret;
>
> if (unlikely(count <= 0))
> return 0;
>
> - old_fs = force_uaccess_begin();
> pagefault_disable();
> ret = strncpy_from_user(dst, unsafe_addr, count);
> pagefault_enable();
> - force_uaccess_end(old_fs);
>
> if (ret >= count) {
> ret = count;
> @@ -216,14 +208,11 @@ long strncpy_from_user_nofault(char *dst, const void
> __user *unsafe_addr,
> */
> long strnlen_user_nofault(const void __user *unsafe_addr, long count)
> {
> - mm_segment_t old_fs;
> int ret;
>
> - old_fs = force_uaccess_begin();
> pagefault_disable();
> ret = strnlen_user(unsafe_addr, count);
> pagefault_enable();
> - force_uaccess_end(old_fs);
>
> return ret;
> }
> diff --git a/mm/memory.c b/mm/memory.c
> index c125c4969913..9a6ebf68a846 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -5256,14 +5256,6 @@ void print_vma_addr(char *prefix, unsigned long ip)
> #if defined(CONFIG_PROVE_LOCKING) || defined(CONFIG_DEBUG_ATOMIC_SLEEP)
> void __might_fault(const char *file, int line)
> {
> - /*
> - * Some code (nfs/sunrpc) uses socket ops on kernel memory while
> - * holding the mmap_lock, this is safe because kernel memory doesn't
> - * get paged out, therefore we'll never actually fault, and the
> - * below annotations will generate false positives.
> - */
> - if (uaccess_kernel())
> - return;
> if (pagefault_disabled())
> return;
> __might_sleep(file, line);
> diff --git a/net/bpfilter/bpfilter_kern.c b/net/bpfilter/bpfilter_kern.c
> index 51a941b56ec3..422ec6e7ccff 100644
Acked-by: Stafford Horne [openrisc, asm-generic]
Thanks!
the get_fs()
> - */
> -#ifndef __access_ok
> -static inline int __access_ok(unsigned long addr, unsigned long size)
> -{
> - return 1;
> -}
> -#endif
> +#include
>
> /*
> * These are the main single-value transfer routines. They automatically
> diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
> index 67e9bc94dc40..2c31667e62e0 100644
> --- a/include/linux/uaccess.h
> +++ b/include/linux/uaccess.h
> @@ -33,13 +33,6 @@ typedef struct {
> /* empty dummy */
> } mm_segment_t;
>
> -#ifndef TASK_SIZE_MAX
> -#define TASK_SIZE_MAXTASK_SIZE
> -#endif
> -
> -#define uaccess_kernel() (false)
> -#define user_addr_max() (TASK_SIZE_MAX)
> -
> static inline mm_segment_t force_uaccess_begin(void)
> {
> return (mm_segment_t) { };
Acked-by: Stafford Horne [openrisc, asm-generic]
Thanks!
Hi Segher,
On Wed, Oct 06, 2021 at 04:27:28PM -0500, Segher Boessenkool wrote:
> On Thu, Oct 07, 2021 at 05:44:00AM +0900, Stafford Horne wrote:
> > You have defined of_get_cpu_hwid to return u64, will this create compiler
> > warnings when since we are storing a u64 into a u32?
&g
On Wed, Oct 06, 2021 at 04:08:38PM -0500, Rob Herring wrote:
> On Wed, Oct 6, 2021 at 3:44 PM Stafford Horne wrote:
> >
> > On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote:
> > > Replace open coded parsing of CPU nodes' 'reg' property with
On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote:
> Replace open coded parsing of CPU nodes' 'reg' property with
> of_get_cpu_hwid().
>
> Cc: Jonas Bonn
> Cc: Stefan Kristiansson
> Cc: Stafford Horne
> Cc: openr...@lists.librecores.org
> Si
On Wed, Apr 07, 2021 at 11:47:49AM +0200, Peter Zijlstra wrote:
> On Wed, Apr 07, 2021 at 08:52:08AM +0900, Stafford Horne wrote:
> > Why doesn't RISC-V add the xchg16 emulation code similar to OpenRISC? For
> > OpenRISC we added xchg16 and xchg8 emulation code to enable qsp
On Wed, Apr 07, 2021 at 12:51:56AM +0800, Boqun Feng wrote:
> Hi,
>
> On Wed, Mar 31, 2021 at 02:30:32PM +, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Some architectures don't have sub-word swap atomic instruction,
> > they only have the full word's one.
> >
> > The sub-word swap on
risk for atomic operations.
>
> This patch cancels the dependency of on qspinlock generic code on
> architecture's xchg16.
>
> Signed-off-by: Guo Ren
> Cc: Arnd Bergmann
> Cc: Jonas Bonn
> Cc: Stefan Kristiansson
> Cc: Stafford Horne
> Cc: openr...@lists.libr
00/kernel/setup.c| 8 +++-
> arch/nds32/kernel/setup.c| 8 ++--
> arch/openrisc/kernel/setup.c | 9 ++---
> 3 files changed, 7 insertions(+), 18 deletions(-)
Hi Mike,
For the openrisc part:
Acked-by: Stafford Horne
> --- a/arch/openrisc/kernel/setup.c
> +++ b/a
ser page tables.
>
> The pte_alloc_one_kernel() is kept back because its implementation on
> openrisc is different than the generic one.
>
> Signed-off-by: Mike Rapoport
Thank's for this.
Acked-by: Stafford Horne
BLE + __pa(pte)));
>
> /* Fill the newly allocated page with PTE'S */
This seems reasonable to me.
Acked-by: Stafford Horne
oc().
Hello Mike,
This looks fine to me. How do you plan to get this merged? Will you be taking
care of the whole series or so you want me to queue this openrisc part?
> Signed-off-by: Mike Rapoport
Acked-by: Stafford Horne
> ---
> arch/openrisc/mm/ioremap.c | 11 --
> include/linux/compiler_types.h | 18 ++
> include/linux/syscalls.h | 4 +++
> 5 files changed, 95 insertions(+), 5 deletions(-)
Hello Paul,
I tested the series out with the new OpenRISC 9.0.0 port and the
-Wattribute-alias warnings are gone. Thank
On Sat, Mar 04, 2017 at 11:15:17AM -0800, H. Peter Anvin wrote:
> On 03/04/17 05:05, Russell King - ARM Linux wrote:
> >>
> >> +static int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
> >> +{
> >> + int op = (encoded_op >> 28) & 7;
> >> + int cmp = (encoded_op >> 24) & 15;
> >> +
31 matches
Mail list logo
