On Tue, Oct 01, 2024 at 12:08:47PM +0200, Michal Suchanek wrote:
> There is no modular user of analyze_instr, and the latter two are only
> used by sstep itself.
As far as I can see, analyze_instr is still used in
arch/powerpc/kvm/emulate_loadstore.c, and that can be included in a
module, e.g., wh
On Wed, Jun 14, 2023 at 10:34:45AM +0800, baomingtong...@208suo.com wrote:
> fix the following coccicheck warning:
>
> arch/powerpc/kvm/book3s_pr.c:424:5-6: Unneeded variable: "r".
>
> Signed-off-by: Mingtong Bao
> ---
> arch/powerpc/kvm/book3s_pr.c | 4 ++--
> 1 file changed, 2 insertions(+),
userspace interfaces for
> POWER9 MMU")
> Signed-off-by: Joel Stanley
Acked-by: Paul Mackerras
This series changes the powerpc KVM code so that HV KVM can fetch
prefixed instructions from the guest in those situations where there
is a need to emulate an instruction, which for HV KVM means emulating
loads and stores to emulated MMIO devices. (Prefixed instructions
were introduced with POWER1
, ppc_inst_t is 32 bits wide, and is turned back
into a u32 by ppc_inst_val, which is an identity operation on those
platforms.
Reviewed-by: Nicholas Piggin
Tested-by: Nicholas Piggin
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_ppc.h | 5 +++--
arch/powerpc/kvm
has not yet been extended to handle prefixed instructions in
all situations where we might need to emulate them, so prevent the
guest from enabling prefixed instructions in the FSCR for now.
Reviewed-by: Nicholas Piggin
Tested-by: Nicholas Piggin
Signed-off-by: Paul Mackerras
---
arch/powerpc
in
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/include/asm/kvm_ppc.h | 32 ++---
arch/powerpc/kvm/book3s.c | 32 +
arch/powerpc/kvm/book3s_64_mmu_hv.c | 14 +--
ar
On Wed, Aug 31, 2022 at 08:44:54AM +0800, Jilin Yuan wrote:
> Delete the redundant word 'that'.
Nack, having two "that"s in a row is intentional. It's "make sure
that" (i.e. bring about the situation described in what follows)
"that many HPTEs" (i.e. the number of HPTEs referenced previously)
"ar
This marks more files and functions that can possibly be called in
real mode as not to be instrumented by KASAN. Most were found by
inspection, except for get_pseries_errorlog() which was reported as
causing a crash in testing.
Reported-by: Nageswara R Sastry
Signed-off-by: Paul Mackerras
all the entry points to the generic
KASAN code are protected with a call to kasan_arch_is_ready().]
Originally-by: Balbir Singh # ppc64 out-of-line radix
version
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
Documentation/powerpc/kasan.txt |
From: Daniel Axtens
KASAN is supported on 32-bit powerpc and the docs should reflect this.
Suggested-by: Christophe Leroy
Reviewed-by: Christophe Leroy
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
Documentation/powerpc/kasan.txt | 12
1 file changed, 12
From: Daniel Axtens
kasan is already implied by the directory name, we don't need to
repeat it.
Suggested-by: Christophe Leroy
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
arch/powerpc/mm/kasan/Makefile | 2 +-
arch/powerpc/mm/kasan/{kasan_init
From: Daniel Axtens
Signed-off-by: Paul Mackerras
---
Documentation/dev-tools/kasan.rst | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/dev-tools/kasan.rst
b/Documentation/dev-tools/kasan.rst
index 8089c559d339..448995c11bee 100644
--- a/Documentation
This patch series implements KASAN on 64-bit POWER with radix MMU,
such as POWER9 or POWER10. Daniel Axtens posted previous versions of
these patches, but is no longer working on KASAN, and I have been
asked to get them ready for inclusion.
Because of various technical difficulties, mostly around
message.]
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/interrupt.h | 52 +---
arch/powerpc/kernel/smp.c| 22 ++--
arch/powerpc/kernel/traps.c | 6 ++--
arch/powerpc/lib/Makefile| 3 ++
a few work-in-progress commits of
Daniel's and wrote the commit message.]
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
arch/powerpc/kexec/Makefile | 2 ++
arch/powerpc/platforms/pseries/Makefile | 3 +++
arch/powerpc/sysdev/xics/xics-common.c | 4 ++--
On Sun, May 15, 2022 at 07:33:52AM +, Christophe Leroy wrote:
>
>
> Le 11/05/2022 à 09:28, Paul Mackerras a écrit :
> > From: Daniel Axtens
> >
> > Implement a limited form of KASAN for Book3S 64-bit machines running under
> > the Radix MMU, supporting onl
This patch series implements KASAN on 64-bit POWER with radix MMU,
such as POWER9 or POWER10. Daniel Axtens posted previous versions of
these patches, but is no longer working on KASAN, and I have been
asked to get them ready for inclusion.
Because of various technical difficulties, mostly around
ot;global_oob_right" test, and it
only fails when CONFIG_KASAN_KUNIT_TEST=m; it passes when the kunit
tests are built in. That is, KASAN is not detecting out-of-bounds
accesses to module-global data.
]
Originally-by: Balbir Singh # ppc64 out-of-line radix
version
Signed-of
From: Daniel Axtens
kasan is already implied by the directory name, we don't need to
repeat it.
Suggested-by: Christophe Leroy
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
arch/powerpc/mm/kasan/Makefile | 2 +-
arch/powerpc/mm/kasan/{kasan_init
From: Daniel Axtens
KASAN is supported on 32-bit powerpc and the docs should reflect this.
Suggested-by: Christophe Leroy
Reviewed-by: Christophe Leroy
Signed-off-by: Daniel Axtens
Signed-off-by: Paul Mackerras
---
Documentation/dev-tools/kasan.rst | 8 ++--
Documentation/powerpc
On Tue, Mar 08, 2022 at 10:23:38PM -0300, Fabiano Rosas wrote:
> This patch adds a new KVM capability to address a crash we're
> currently having inside the nested guest kernel when running with
> GTSE disabled in the nested hypervisor.
I think the patch needs to add a description of KVM_CAP_PPC_G
On Sat, Jun 19, 2021 at 09:26:16AM -0500, Segher Boessenkool wrote:
> On Fri, Jun 18, 2021 at 01:44:16PM +1000, Paul Mackerras wrote:
> > Microwatt currently runs with MSR[HV] = 0,
>
> That isn't compliant though? If your implementation does not have LPAR
> it must set
hich available in the standalone Microwatt FPGA.
> >
> > Signed-off-by: Benjamin Herrenschmidt
> > Signed-off-by: Paul Mackerras
...
> > +#ifdef CONFIG_PPC_EARLY_DEBUG_MICROWATT
> > +
> > +#define UDBG_UART_MW_ADDR ((void __iomem *)0xc0002000)
> > +
> >
Microwatt's hardware RNG is accessed using the DARN instruction.
Signed-off-by: Paul Mackerras
---
arch/powerpc/platforms/microwatt/Kconfig | 1 +
arch/powerpc/platforms/microwatt/Makefile | 2 +-
arch/powerpc/platforms/microwatt/rng.c| 48 +++
3 files change
This series of patches adds support for the Microwatt soft-core.
Microwatt is an open-source 64-bit Power ISA processor written in VHDL
which targets medium-sized FPGAs such as the Xilinx Artix-7 or the
Lattice ECP5. Microwatt currently implements the scalar fixed plus
floating-point subset of Pow
From: Benjamin Herrenschmidt
This is a simple native ICS backend that matches the layout of
the Microwatt implementation of ICS.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 18 ++
arch/powerpc/platforms/microwatt/Kconfig
From: Benjamin Herrenschmidt
Just like any other embedded platform.
Add an empty soc node.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 7 +++
arch/powerpc/platforms/microwatt/setup.c | 8
2 files changed, 15
radix tree but not
hypervisor mode or nested radix translation.
This adds a new machine type to support FPGA-based SoCs with a
Microwatt core. CONFIG_MATH_EMULATION can be selected for Microwatt
SOCs which don't have the FPU.
Signed-off-by: Paul Mackerras
---
arch/powerpc/Kc
From: Benjamin Herrenschmidt
This fixes the core devtree.c functions and the ns16550 UART backend.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/devtree.c | 59 +
arch/powerpc/boot/ns16550.c | 9 --
2 files
From: Joel Stanley
This allows microwatt's kernel to be built with an embedded device tree.
Load to arch/powerpc/boot/dtbImage.microwatt to 0x50:
mw_debug -b fpga stop load arch/powerpc/boot/dtbImage.microwatt 50 start
Signed-off-by: Joel Stanley
Signed-off-by: Paul Mack
Microwatt currently runs with MSR[HV] = 0, hence the usable-privilege
properties don't have bit 2 (for HV support) set, and we need the
/chosen/ibm,architecture-vec-5 property.
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 98 +
1
From: Benjamin Herrenschmidt
This adds support to the Microwatt platform to use the standard
16550-style UART which available in the standalone Microwatt FPGA.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 27
Signed-off-by: Paul Mackerras
---
arch/powerpc/configs/microwatt_defconfig | 98
1 file changed, 98 insertions(+)
create mode 100644 arch/powerpc/configs/microwatt_defconfig
diff --git a/arch/powerpc/configs/microwatt_defconfig
b/arch/powerpc/configs
On Thu, Jun 17, 2021 at 02:41:28PM +1000, Michael Ellerman wrote:
> Paul Mackerras writes:
> >
>
> Little bit of change log never hurts :)
>
> > Signed-off-by: Paul Mackerras
> > ---
> > arch/powerpc/boot/dts/microwatt.dts | 105
On Wed, Jun 16, 2021 at 01:40:07PM -0500, Segher Boessenkool wrote:
> Hi Paul,
>
> On Tue, Jun 15, 2021 at 08:57:43AM +1000, Paul Mackerras wrote:
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -422,7 +422,7 @@ config HUGETLB_PAGE_SIZE
On Wed, Jun 16, 2021 at 11:16:02PM +1000, Michael Ellerman wrote:
> Nicholas Piggin writes:
> > I would be happier if you didn't change this (or at least put it in its
> > own patch explaining why it's not going to slow down other platforms).
>
> It would essentially be a revert of 01c9348c7620
This ensures that we don't get a decrementer interrupt arriving before
we have set up a handler for it.
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/microwatt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/boot/microwatt.c b/arch/powerpc/boot/microwatt.c
From: Benjamin Herrenschmidt
This is a simple native ICS backend that matches the layout of
the Microwatt implementation of ICS.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/boot/dts/microwatt.dts | 18 ++
arch/powerpc/platforms/microwatt/Kconfig | 2 +
arch/powerpc/platforms
or now, as that is in the
range of SPR numbers assigned for experimental use. PRTBL is only
written when we have neither the FW_FEATURE_LPAR feature nor the
CPU_FTR_HVMODE feature.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/mm/book3s64/radix
From: Benjamin Herrenschmidt
Just like any other embedded platform.
Add an empty soc node.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/boot/dts/microwatt.dts | 7 +++
arch/powerpc/platforms/microwatt/setup.c | 8
2 files changed, 15 insertions(+)
diff --git a/arc
This series of patches adds support for the Microwatt soft-core.
Microwatt is an open-source 64-bit Power ISA processor written in VHDL
which targets medium-sized FPGAs such as the Xilinx Artix-7 or the
Lattice ECP5. Microwatt currently implements the scalar fixed plus
floating-point subset of Pow
This is accessed using the DARN instruction and should probably be
done more generically.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/archrandom.h | 12 +-
arch/powerpc/platforms/microwatt/Kconfig | 1 +
arch/powerpc/platforms/microwatt/Makefile | 2 +-
arch/powerpc
From: Benjamin Herrenschmidt
This adds support to the Microwatt platform to use the standard
1655-style UART which available in the standalone Microwatt FPGA.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/boot/dts/microwatt.dts | 25 ---
arch/powerpc/kernel/udbg_16550
From: Benjamin Herrenschmidt
This fixes the core devtree.c functions and the ns16550 UART backend.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/boot/devtree.c | 59 +
arch/powerpc/boot/ns16550.c | 9 --
2 files changed, 41 insertions(+), 27 de
Microwatt is a FPGA-based implementation of the Power ISA. It
currently only implements little-endian 64-bit mode, and does
not (yet) support SMP, VMX, VSX or transactional memory.
This adds a new machine type to support FPGA-based SoCs with a
Microwatt core.
Signed-off-by: Paul Mackerras
From: Joel Stanley
This allows microwatt's kernel to be built with an embedded device tree.
Load to arch/powerpc/boot/dtbImage.microwatt to 0x50:
mw_debug -b fpga stop load arch/powerpc/boot/dtbImage.microwatt 50 start
Signed-off-by: Joel Stanley
---
arch/powerpc/boot/Makefile|
Signed-off-by: Paul Mackerras
---
arch/powerpc/configs/microwatt_defconfig | 98
1 file changed, 98 insertions(+)
create mode 100644 arch/powerpc/configs/microwatt_defconfig
diff --git a/arch/powerpc/configs/microwatt_defconfig
b/arch/powerpc/configs
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/dts/microwatt.dts | 105
1 file changed, 105 insertions(+)
create mode 100644 arch/powerpc/boot/dts/microwatt.dts
diff --git a/arch/powerpc/boot/dts/microwatt.dts
b/arch/powerpc/boot/dts/microwatt.dts
new file
.
Signed-off-by: Paul Mackerras
---
arch/powerpc/perf/generic-compat-pmu.c | 170 +++--
1 file changed, 134 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/perf/generic-compat-pmu.c
b/arch/powerpc/perf/generic-compat-pmu.c
index eb8a6aaf4cc1..695975227e60 100644
--- a
On Tue, May 04, 2021 at 03:26:24PM +1000, Nicholas Piggin wrote:
> Excerpts from Paul Mackerras's message of May 4, 2021 2:28 pm:
> > On Sat, May 01, 2021 at 11:58:36AM +1000, Nicholas Piggin wrote:
> >> Excerpts from Fabiano Rosas's message of April 16, 2021 9:09 am:
> >> > As one of the arguments
On Sat, May 01, 2021 at 11:58:36AM +1000, Nicholas Piggin wrote:
> Excerpts from Fabiano Rosas's message of April 16, 2021 9:09 am:
> > As one of the arguments of the H_ENTER_NESTED hypercall, the nested
> > hypervisor (L1) prepares a structure containing the values of various
> > hypervisor-privil
On Mon, Apr 05, 2021 at 11:19:38AM +1000, Nicholas Piggin wrote:
> Radix guest support will be removed from the P7/8 path, so disallow
> dependent threads mode on P9.
Dependent threads mode on P9 was added in order to support the mode
where for security reasons you want to restrict the vcpus that
On Mon, Apr 05, 2021 at 11:19:30AM +1000, Nicholas Piggin wrote:
> Almost all logic is moved to C, by introducing a new in_guest mode for
> the P9 path that branches very early in the KVM interrupt handler to
> P9 exit code.
>
> The main P9 entry and exit assembly is now only about 160 lines of lo
On Mon, Apr 05, 2021 at 11:19:16AM +1000, Nicholas Piggin wrote:
> Like the earlier patch for hcalls, KVM interrupt entry requires a
> different calling convention than the Linux interrupt handlers
> set up. Move the code that converts from one to the other into KVM.
I don't see where you do anyth
On Tue, Apr 06, 2021 at 12:44:45PM +1000, Nicholas Piggin wrote:
> Excerpts from Nicholas Piggin's message of April 5, 2021 11:19 am:
> > The code being executed in KVM_GUEST_MODE_SKIP is hypervisor code with
> > MSR[IR]=0, so the faults of concern are the d-side ones caused by access
> > to guest
On Tue, Mar 23, 2021 at 11:02:32AM +1000, Nicholas Piggin wrote:
> Move the GUEST_MODE_SKIP logic into KVM code. This is quite a KVM
> internal detail that has no real need to be in common handlers.
>
> Also add a comment explaining why this thing exists.
[snip]
> diff --git a/arch/powerpc/kvm/b
type of exit handler.
>
> Reviewed-by: Daniel Axtens
> Reviewed-by: Fabiano Rosas
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
On Tue, Mar 23, 2021 at 11:02:34AM +1000, Nicholas Piggin wrote:
> System calls / hcalls have a different calling convention than
> other interrupts, so there is code in the KVMTEST to massage these
> into the same form as other interrupt handlers.
>
> Move this work into the KVM hcall handler. Th
arn if it's not present.
Will warn if it *is* present, surely?
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
t's not present.
>
> Reviewed-by: Daniel Axtens
> Reviewed-by: Fabiano Rosas
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
t; Reviewed-by: Fabiano Rosas
> Signed-off-by: Nicholas Piggin
It might be worth noting in the commit message that the 0x1300
interrupt was dropped from the architecture a long time ago and is not
generated by P7, P8, P9 or P10.
Acked-by: Paul Mackerras
On Tue, Mar 23, 2021 at 11:02:27AM +1000, Nicholas Piggin wrote:
> Cell does not support KVM.
>
> Reviewed-by: Fabiano Rosas
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
On Tue, Mar 23, 2021 at 11:02:26AM +1000, Nicholas Piggin wrote:
> This config option causes the warning in init_default_hcalls to fire
> because the TCE handlers are in the default hcall list but not
> implemented.
>
> Reviewed-by: Daniel Axtens
> Signed-off-by: Nicholas Piggi
On Tue, Mar 23, 2021 at 11:02:24AM +1000, Nicholas Piggin wrote:
> This SPR is set to 0 twice when exiting the guest.
>
> Suggested-by: Fabiano Rosas
> Reviewed-by: Daniel Axtens
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
On Tue, Mar 23, 2021 at 11:02:25AM +1000, Nicholas Piggin wrote:
> The va argument is not used in the function or set by its asm caller,
> so remove it to be safe.
>
> Reviewed-by: Daniel Axtens
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
On Tue, Mar 23, 2021 at 11:02:23AM +1000, Nicholas Piggin wrote:
> This bit only applies to hash partitions.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kvm/book3s_hv.c| 6 ++
> arch/powerpc/kvm/book3s_hv_nested.c | 3 +--
> 2 files changed, 7 insertions(+), 2 deletions(-
ter it here too.
>
> Suggested-by: Fabiano Rosas
> Signed-off-by: Nicholas Piggin
Acked-by: Paul Mackerras
On Tue, Mar 23, 2021 at 11:02:21AM +1000, Nicholas Piggin wrote:
> Guest LPCR depends on hardware type, and future changes will add
> restrictions based on errata and guest MMU mode. Move this logic
> to a common function and use it for the cases where the guest
> wants to update its LPCR (or the L
On Tue, Mar 23, 2021 at 11:02:20AM +1000, Nicholas Piggin wrote:
> This will get a bit more complicated in future patches. Move it
> into the helper function.
This does change L1-visible behaviour, because now the L1 hypervisor
can see the LPCR bits that L0 is using, whereas previously it couldn't
On Mon, Mar 08, 2021 at 06:18:47PM +1000, Nicholas Piggin wrote:
> Excerpts from Fabiano Rosas's message of March 6, 2021 9:10 am:
> > As one of the arguments of the H_ENTER_NESTED hypercall, the nested
> > hypervisor (L1) prepares a structure containing the values of various
> > hypervisor-privile
On Mon, Jan 18, 2021 at 04:28:07PM +1000, Nicholas Piggin wrote:
> The slbmte instruction is legal in radix mode, including radix guest
> mode. This means radix guests can load the SLB with arbitrary data.
>
> KVM host does not clear the SLB when exiting a guest if it was a
> radix guest, which wo
t; ./arch/powerpc/kvm/booke.c:507:6-16: WARNING: Comparison to bool
>
> Reported-by: Tosk Robot
> Signed-off-by: Kaixu Xia
Acked-by: Paul Mackerras
ARNING: Assignment of 0/1 to bool
> variable
>
> Reported-by: Tosk Robot
> Signed-off-by: Kaixu Xia
Acked-by: Paul Mackerras
d 't' is missing their MSB:
> msgtype: ((arg >> 27) & 0xf) : Gets (RB) 33:36, missing bit 32
> t: (arg &= 0x3f) : Gets (RB) 58:63, missing bit 57
>
> Fixes this by applying the correct mask.
>
> Signed-off-by: Leonardo Bras
Acked-by: Paul Mackerras
On Fri, Dec 11, 2020 at 12:16:39PM +1100, David Gibson wrote:
> On Thu, Dec 10, 2020 at 09:54:18AM +0530, Bharata B Rao wrote:
> > On Wed, Dec 09, 2020 at 03:15:42PM +1100, Paul Mackerras wrote:
> > > On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
On Tue, Nov 24, 2020 at 04:29:53PM +0530, Ravi Bangoria wrote:
> Introduce KVM_CAP_PPC_DAWR1 which can be used by Qemu to query whether
> kvm supports 2nd DAWR or not.
This should be described in Documentation/virt/kvm/api.rst.
Strictly speaking, it should be a capability which is disabled by
def
On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
> Implements H_RPT_INVALIDATE hcall and supports only nested case
> currently.
>
> A KVM capability KVM_CAP_RPT_INVALIDATE is added to indicate the
> support for this hcall.
I have a couple of questions about this patch:
1. Is this s
On Sat, Sep 19, 2020 at 09:29:25AM +0800, Qinglang Miao wrote:
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Qinglang Miao
Thanks, applied.
Paul.
On Fri, Sep 11, 2020 at 12:53:45PM +0200, Greg Kurz wrote:
> ENOTSUPP is a linux only thingy, the value of which is unknown to
> userspace, not to be confused with ENOTSUP which linux maps to
> EOPNOTSUPP, as permitted by POSIX [1]:
>
> [EOPNOTSUPP]
> Operation not supported on socket. The type of
On Fri, Sep 11, 2020 at 01:16:07AM -0300, Fabiano Rosas wrote:
> The current nested KVM code does not support HPT guests. This is
> informed/enforced in some ways:
>
> - Hosts < P9 will not be able to enable the nested HV feature;
>
> - The nested hypervisor MMU capabilities will not contain
>
On Sat, Sep 19, 2020 at 03:12:30PM +0800, Jing Xiangfeng wrote:
> The variable ret is being initialized with '-ENOMEM' that is meaningless.
> So remove it.
>
> Signed-off-by: Jing Xiangfeng
Thanks, applied.
Paul.
On Mon, Sep 21, 2020 at 11:22:11AM +, Wang Wensheng wrote:
> Build the kernel with `C=2`:
> arch/powerpc/kvm/book3s_hv_nested.c:572:25: warning: symbol
> 'kvmhv_alloc_nested' was not declared. Should it be static?
> arch/powerpc/kvm/book3s_64_mmu_radix.c:350:6: warning: symbol
> 'kvmppc_radix_s
sh mode PowerPC KVM guests.
>
> Cc: linux-ker...@vger.kernel.org
> Cc: kvm-...@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: Paul Mackerras
> Cc: Michael Ellerman
> Cc: Jonathan Corbet
> Reviewed-by: Randy Dunlap
> Signed-off-by: Satheesh Rajendran
> -
: Nicholas Piggin
For the KVM part:
Acked-by: Paul Mackerras
On Wed, Sep 02, 2020 at 06:00:24PM +1000, Jordan Niethe wrote:
> On Wed, Sep 2, 2020 at 4:18 PM Paul Mackerras wrote:
> >
> > On Thu, Aug 20, 2020 at 01:39:21PM +1000, Jordan Niethe wrote:
> > > The ppc_inst type was added to help cope with the addition of prefixed
>
On Thu, Aug 20, 2020 at 01:39:22PM +1000, Jordan Niethe wrote:
> There are two main places where instructions are loaded from the guest:
> * Emulate loadstore - such as when performing MMIO emulation
> triggered by an HDSI
> * After an HV emulation assistance interrupt (e40)
>
> If i
On Thu, Aug 20, 2020 at 01:39:21PM +1000, Jordan Niethe wrote:
> The ppc_inst type was added to help cope with the addition of prefixed
> instructions to the ISA. Convert KVM to use this new type for dealing
> wiht instructions. For now do not try to add further support for
> prefixed instructions.
On Thu, Jul 16, 2020 at 05:07:12PM +0800, Qinglang Miao wrote:
> From: Chen Huang
>
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Chen Huang
For the arch/powerpc/kvm part:
Acked-by: Paul Mackerras
I expect Michael Ellerman will take the patch t
On Thu, Jul 23, 2020 at 03:50:51PM +0530, Ravi Bangoria wrote:
> Patch #1, #2 and #3 enables p10 2nd DAWR feature for Book3S kvm guest. DAWR
> is a hypervisor resource and thus H_SET_MODE hcall is used to set/unset it.
> A new case H_SET_MODE_RESOURCE_SET_DAWR1 is introduced in H_SET_MODE hcall
> f
On Thu, Jul 23, 2020 at 03:50:53PM +0530, Ravi Bangoria wrote:
> kvm code assumes single DAWR everywhere. Add code to support 2nd DAWR.
> DAWR is a hypervisor resource and thus H_SET_MODE hcall is used to set/
> unset it. Introduce new case H_SET_MODE_RESOURCE_SET_DAWR1 for 2nd DAWR.
Is this the s
On Thu, Jul 23, 2020 at 03:50:52PM +0530, Ravi Bangoria wrote:
> Power10 is introducing second DAWR. Use real register names (with
> suffix 0) from ISA for current macros and variables used by kvm.
Most of this looks fine, but I think we should not change the existing
names in arch/powerpc/include
On Mon, Jul 27, 2020 at 11:07:13AM -0700, Ram Pai wrote:
> The time to switch a VM to Secure-VM, increases by the size of the VM.
> A 100GB VM takes about 7minutes. This is unacceptable. This linear
> increase is caused by a suboptimal behavior by the Ultravisor and the
> Hypervisor. The Ultravis
On Mon, Jul 27, 2020 at 12:24:27PM -0700, Ram Pai wrote:
> From: Laurent Dufour
>
> When doing memory hotplug on a secure VM, the secure pages are not well
> cleaned from the secure device when dropping the memslot. This silent
> error, is then preventing the SVM to reboot properly after the fol
On Tue, Jun 23, 2020 at 09:14:16PM +0800, Tianjia Zhang wrote:
> In the current kvm version, 'kvm_run' has been included in the 'kvm_vcpu'
> structure. For historical reasons, many kvm-related function parameters
> retain the 'kvm_run' and 'kvm_vcpu' parameters at the same time. This
> patch does a
On Tue, Jun 02, 2020 at 03:53:25PM +1000, Alistair Popple wrote:
> Adds support for emulating ISAv3.1 guests by adding the appropriate PCR
> and FSCR bits.
>
> Signed-off-by: Alistair Popple
Thanks, patch applied to my kvm-ppc-next branch.
Paul.
On Tue, Jun 09, 2020 at 12:12:29PM +1000, Alexey Kardashevskiy wrote:
> The kvm_vcpu_read_guest/kvm_vcpu_write_guest used for nested guests
> eventually call srcu_dereference_check to dereference a memslot and
> lockdep produces a warning as neither kvm->slots_lock nor
> kvm->srcu lock is held and
On Mon, Jun 08, 2020 at 01:57:14PM +0200, Cédric Le Goater wrote:
> POWER8 and POWER9 have 12-bit LPIDs. Change LPID_RSVD to support up to
> (4096 - 2) guests on these processors. POWER7 is kept the same with a
> limitation of (1024 - 2), but it might be time to drop KVM support for
> POWER7.
>
>
On Thu, Jul 16, 2020 at 01:32:13AM -0700, Ram Pai wrote:
> An instruction accessing a mmio address, generates a HDSI fault. This fault
> is
> appropriately handled by the Hypervisor. However in the case of secureVMs,
> the
> fault is delivered to the ultravisor.
>
> Unfortunately the Ultraviso
On Wed, Jul 22, 2020 at 07:39:26AM +0530, Athira Rajeev wrote:
>
>
> > On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote:
> >
> > On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
> >> Currently `kvm_vcpu_arch` stores all Monitor Mode Control regist
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