st skipped on line 266: /dev/papr-vpd not present
Signed-off-by: R Nageswara Sastry
---
tools/testing/selftests/powerpc/papr_vpd/papr_vpd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/powerpc/papr_vpd/papr_vpd.c
b/tools/testing/selftests/powerp
On 15/08/23 4:57 pm, Nayna Jain wrote:
Update Kconfig to enable machine keyring and limit to CA certificates
on PowerVM. Only key signing CA keys are allowed.
Signed-off-by: Nayna Jain
Reviewed-and-tested-by: Mimi Zohar
Reviewed-by: Jarkko Sakkinen
Tested with trustedcadb, moduledb scena
On 15/08/23 4:57 pm, Nayna Jain wrote:
On secure boot enabled PowerVM LPAR, third party code signing keys are
needed during early boot to verify signed third party modules. These
third party keys are stored in moduledb object in the Platform
KeyStore (PKS).
Load third party code signing keys
On 15/08/23 4:57 pm, Nayna Jain wrote:
trust_moklist() is specific to UEFI enabled systems. Other platforms
rely only on the Kconfig.
Define a generic wrapper named imputed_trust_enabled().
Signed-off-by: Nayna Jain
Reviewed-off-by: Mimi Zohar
Tested with trustedcadb, moduledb scenarios
On 15/08/23 4:57 pm, Nayna Jain wrote:
trust_mok variable is accessed within a single function locally.
Change trust_mok from global to local static variable.
Signed-off-by: Nayna Jain
Reviewed-and-tested-by: Mimi Zohar
Reviewed-by: Jarkko Sakkinen
Tested with trustedcadb, moduledb sce
On 15/08/23 4:57 pm, Nayna Jain wrote:
On non-UEFI platforms, handle restrict_link_by_ca failures differently.
Certificates which do not satisfy CA restrictions on non-UEFI platforms
are ignored.
Signed-off-by: Nayna Jain
Reviewed-and-tested-by: Mimi Zohar
Acked-by: Jarkko Sakkinen
Tes
On 15/08/23 4:57 pm, Nayna Jain wrote:
Keys that derive their trust from an entity such as a security officer,
administrator, system owner, or machine owner are said to have "imputed
trust". CA keys with imputed trust can be loaded onto the machine keyring.
The mechanism for loading these keys
On 08/06/23 5:34 pm, Nayna Jain wrote:
On PowerVM guest, variable data is prefixed with 8 bytes of timestamp.
Extract ESL by stripping off the timestamp before passing to ESL parser.
Fixes: 4b3e71e9a34c ("integrity/powerpc: Support loading keys from PLPKS")
Cc: sta...@vger.kenrnel.org # v6.3
On 17/05/23 1:19 pm, Michael Ellerman wrote:
Nageswara reported that /proc/self/status was showing "vulnerable" for
the Speculation_Store_Bypass feature on Power10, eg:
$ grep Speculation_Store_Bypass: /proc/self/status
Speculation_Store_Bypass: vulnerable
But at the same time th
On 22/03/23 9:23 am, Russell Currey wrote:
fail_iommu_setup() registers the fail_iommu_bus_notifier struct to both
PCI and VIO buses. struct notifier_block is a linked list node, so this
causes any notifiers later registered to either bus type to also be
registered to the other since they sha
2048 CPUs. Consider raising MAX_NR_CPUS
Failed to initialize parallel data streaming masks
<<>>
With this fix, if -C is given a non-exsiting CPU, perf
record will fail with:
<<>>
./perf record -C 50 ls
Failed to initialize parallel data streaming masks
ons
page-faults
cycles
instructions
branches
branch-misses
0.001192373 seconds time elapsed
<<>>
Reported-by: Nageswara Sastry
Tested-by: Nageswara Sastry
Signed-off-by: Athira Rajeev
---
tools/perf/util/affinity.c | 8 +++-
On 25/02/22 12:08 pm, kajoljain wrote:
On 2/25/22 11:25, Nageswara Sastry wrote:
On 17/02/22 10:03 pm, Kajol Jain wrote:
Patchset adds performance stats reporting support for nvdimm.
Added interface includes support for pmu register/unregister
functions. A structure is added called
On 17/02/22 10:03 pm, Kajol Jain wrote:
Patchset adds performance stats reporting support for nvdimm.
Added interface includes support for pmu register/unregister
functions. A structure is added called nvdimm_pmu to be used for
adding arch/platform specific data such as cpumask, nvdimm device
On 13/12/21 10:12 pm, Sachin Sant wrote:
Mitigation patching test iterates over a set of mitigations irrespective
of whether a certain mitigation is supported/available in the kernel.
This causes following messages on a kernel where some mitigations
are unavailable:
Spawned threads enablin
On 07/12/21 8:22 pm, Arnaldo Carvalho de Melo wrote:
Em Fri, Dec 03, 2021 at 07:50:37AM +0530, Athira Rajeev escreveu:
Sort key p_stage_cyc is used to present the latency
cycles spend in pipeline stages. perf tool has local
p_stage_cyc sort key to display this info. There is no
global variant
On 25/11/21 8:18 am, Athira Rajeev wrote:
Sort key p_stage_cyc is used to present the latency
cycles spend in pipeline stages. perf tool has local
p_stage_cyc sort key to display this info. There is no
global variant available for this sort key. local variant
shows latency in a sinlge sample,
On 13/08/21 1:51 pm, Kajol Jain wrote:
H_GetPerformanceCounterInfo (0xF080) hcall returns the counter data in the
result buffer. Result buffer has specific format defined in the PAPR
specification. One of the field is counter offset and width of the counter
data returned.
Counter data are ret
On 18/08/21 10:45 pm, Kajol Jain wrote:
Minor optimization in the 'perf_instruction_pointer' function code by
making use of stack siar instead of mfspr.
Fixes: 75382aa72f06 ("powerpc/perf: Move code to select SIAR or pt_regs
into perf_read_regs")
Signed-off-by: Kajol Jain
Tested this patc
On 21/07/21 11:18 am, Athira Rajeev wrote:
Running perf fuzzer showed below in dmesg logs:
"Can't find PMC that caused IRQ"
This means a PMU exception happened, but none of the PMC's (Performance
Monitor Counter) were found to be overflown. There are some corner cases
that clears the PMCs aft
Tested by creating perf-script.py using perf script
and priting the iregs. Seen more values with this patch.
Tested-by: Nageswara R Sastry
On 28/06/21 11:53 am, Kajol Jain wrote:
Commit 48a1f565261d ("perf script python: Add more PMU fields
to event handler dict") added functionality to repor
Test scenarios:
1. With 'perf list metric' and 'perf list metricgroup' - can see metrics
2. Run all the metrics with perf stat with -M option and --metric-only
-M option
The above test scenarios automated with avocado framework, pull request
title: perf_metric.py: Add perf metric test case
On 20/06/21 8:15 pm, Athira Rajeev wrote:
Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps
> On 14-Jun-2021, at 10:53 AM, Kajol Jain wrote:
>
> Patchset adds performance stats reporting support for nvdimm.
> Added interface includes support for pmu register/unregister
> functions. A structure is added called nvdimm_pmu to be used for
> adding arch/platform specific data such as supp
> On 25-May-2021, at 7:21 PM, Athira Rajeev wrote:
>
> The "no_handler_test" in ebb selftests attempts to read the PMU
> registers after closing of the event via helper function
> "dump_ebb_state". With the MMCR0 control bit (PMCCEXT) in ISA v3.1,
> read access to group B registers is restricte
> On 25-May-2021, at 8:57 PM, Paul A. Clarke wrote:
>>
> I lost the original message, but Nageswara Sastry said:
>> 1. Extracted all the 244 events from the patch.
>> 2. Check them in 'perf list' - all 244 events found
>> 3. Ran all the events with
Tested patch with the following steps:
1. Extracted all the 244 events from the patch.
2. Check them in 'perf list' - all 244 events found
3. Ran all the events with 'perf stat -e "event name" sleep 1', all ran fine.
No errors were seen in 'dmesg'
Tested-by: Nageswara R Sastry
> On 25-May
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