allowed to
enumerate the bus.
Cc: Minghuan Lian
Signed-off-by: Aaron Sierra
---
Documentation/devicetree/bindings/pci/fsl,pci.txt | 27 +++
arch/powerpc/sysdev/fsl_pci.c | 3 ++-
2 files changed, 29 insertions(+), 1 deletion(-)
create mode 100644 Doc
- Original Message -
> From: "Scott Wood"
> Sent: Tuesday, August 26, 2014 3:48:51 PM
>
> On Tue, 2014-08-26 at 12:31 -0500, Aaron Sierra wrote:
> > Freescale's QorIQ T Series processors support 8 IFC chip selects
> > within a memory map bac
- Original Message -
> From: "Scott Wood"
> Sent: Tuesday, August 26, 2014 3:52:56 PM
>
> On Mon, 2014-08-25 at 18:54 -0500, Aaron Sierra wrote:
> > The following commit prevents the MPC8548E on the XPedite5200 PrPMC
> > module from enumerating its PCI/P
Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.
Signed-off-by: Aaron Sierra
---
drivers/memory/fsl_ifc.c| 2 +-
drivers/mtd/nand/fsl_ifc_nand.c
allowed to
enumerate the bus.
Cc: Minghuan Lian
Signed-off-by: Aaron Sierra
---
.../bindings/pci/fsl,pci-agent-force-enum.txt | 27 ++
arch/powerpc/sysdev/fsl_pci.c | 3 ++-
2 files changed, 29 insertions(+), 1 deletion(-)
create mode 100644
Doc
- Original Message -
> From: "Scott Wood"
> To: "Aaron Sierra"
> Cc: linuxppc-dev@lists.ozlabs.org, "Minghuan Lian"
>
> Sent: Friday, August 22, 2014 1:36:31 PM
> Subject: Re: [PATCH] powerpc: fsl_pci: Fix PCI/PCI-X regression
>
>
- Original Message -
> From: "Scott Wood"
> Sent: Thursday, August 21, 2014 5:01:46 PM
>
> On Thu, 2014-08-21 at 16:54 -0500, Aaron Sierra wrote:
> > - Original Message -
> > > From: "Scott Wood"
> > > Sent: Thursday, Augus
- Original Message -
> From: "Scott Wood"
> Sent: Thursday, August 21, 2014 4:19:56 PM
>
> On Wed, 2014-08-20 at 18:51 -0500, Aaron Sierra wrote:
> > @@ -520,9 +520,22 @@ int fsl_add_bridge(struct platform_device *pdev, int
> > is_primary)
>
ed MONARCH# signal. If firmware
has determined that enumeration should be allowed, then it will set the
bridge's Bus Master bit in the Command register.
Without firmware intervention, the Bus Master bit defaults to 1 in Host
mode and 0 in Agent mode.
Cc: Minghuan Lian
Signed-off-by: Aaron Si
- Original Message -
> From: "Gokul C G"
> Sent: Tuesday, August 19, 2014 9:43:38 AM
>
> HI,
>
> I am facing problem with PCIE driver in new Linux kernel compiled for powerpc
> architecture (Big endian) ,freescales P2040 processor.I was using old kernel
> Linux version 3.0.48 previously
> >> -#define FSL_IFC_BANK_COUNT 4
> >> +#define FSL_IFC_BANK_COUNT 8
> > First please modify fsl_ifc_nand.c to limit itself to the number of
> > banks it dynamically determines are present based on the IFC version.
> >
> >
>
> Number of available bank/chip select are defined by SoC and it is
> in
Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.
Signed-off-by: Aaron Sierra
---
include/linux/fsl_ifc.h | 10 +-
1 file changed, 5 insertions(+), 5 dele
ff-by: Aaron Sierra
---
include/linux/fsl_ifc.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index f49ddb1..84d60cb 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -781,13 +781,13 @@ struct fsl_ifc
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