[V3 4/4] tools/perf: Add perf tools support to expose instruction and data address registers as part of extended regs

Patch enables presenting of Sampled Instruction Address Register (SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended regsiters for perf tool. Add these SPR's to sample_reg_mask in the tool side (to use with -I? option). Signed-off-by: Athira Rajeev --- tools/arch/powerpc/inc

[V3 3/4] powerpc/perf: Expose instruction and data address registers as part of extended regs

Patch adds support to include Sampled Instruction Address Register (SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended registers. Update the definition of PERF_REG_PMU_MASK_300/31 and PERF_REG_EXTENDED_MAX to include these SPR's. Signed-off-by: Athira Rajeev Reviewed-by: Dani

[V3 2/4] tools/perf: Refactor the code definition of perf reg extended mask in tools side header file

PERF_REG_PMU_MASK_300 and PERF_REG_PMU_MASK_31 defines the mask value for extended registers. Current definition of these mask values uses hex constant and does not use registers by name, making it less readable. Patch refactor the macro values in perf tools side header file by or'ing together the

[V3 1/4] powerpc/perf: Refactor the code definition of perf reg extended mask

PERF_REG_PMU_MASK_300 and PERF_REG_PMU_MASK_31 defines the mask value for extended registers. Current definition of these mask values uses hex constant and does not use registers by name, making it less readable. Patch refactor the macro values by or'ing together the actual register value constants

[V3 0/4] powerpc/perf: Add instruction and data address registers to extended regs

Patch set adds PMU registers namely Sampled Instruction Address Register (SIAR) and Sampled Data Address Register (SDAR) as part of extended regs in PowerPC. These registers provides the instruction/data address and adding these to extended regs helps in debug purposes. Patch 1/4 and 2/4 refactors

Re: [PATCH v3 0/4] Add mem_hops field in perf_mem_data_src structure

On Wed, Oct 06, 2021 at 07:36:50PM +0530, Kajol Jain wrote: > Kajol Jain (4): > perf: Add comment about current state of PERF_MEM_LVL_* namespace and > remove an extra line > perf: Add mem_hops field in perf_mem_data_src structure > tools/perf: Add mem_hops field in perf_mem_data_src str

Re: [PATCH 03/12] ARM: broadcom: Use of_get_cpu_hwid()

On 10/6/2021 9:43 AM, Rob Herring wrote: Replace open coded parsing of CPU nodes 'reg' property with of_get_cpu_hwid(). Cc: Florian Fainelli Cc: Ray Jui Cc: Scott Branden Cc: bcm-kernel-feedback-l...@broadcom.com Cc: Russell King Signed-off-by: Rob Herring Acked-by: Florian Fainelli -

Re: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support

On 10/6/2021 9:43 AM, Rob Herring wrote: The first 10 patches add a new function, of_get_cpu_hwid(), which parses CPU DT node 'reg' property, and then use it to replace all the open coded versions of parsing CPU node 'reg' properties. The last 2 patches add support for populating the cacheinf

Re: [PATCH] Documentation: Fix typo in testing/sysfs-class-cxl

On 7/10/21 2:50 am, Sohaib Mohamed wrote: Remove repeated words: "the the lowest" and "this this kernel" Signed-off-by: Sohaib Mohamed Thanks for catching this. Acked-by: Andrew Donnellan -- Andrew Donnellan OzLabs, ADL Canberra a...@linux.ibm.com IBM Australia Lim

Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()

Hi Segher, On Wed, Oct 06, 2021 at 04:27:28PM -0500, Segher Boessenkool wrote: > On Thu, Oct 07, 2021 at 05:44:00AM +0900, Stafford Horne wrote: > > You have defined of_get_cpu_hwid to return u64, will this create compiler > > warnings when since we are storing a u64 into a u32? > > > > It seems

Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()

On Thu, Oct 07, 2021 at 05:44:00AM +0900, Stafford Horne wrote: > You have defined of_get_cpu_hwid to return u64, will this create compiler > warnings when since we are storing a u64 into a u32? > > It seems only if we make with W=3. Yes. This is done by -Wconversion, "Warn for implicit conversi

Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()

On Wed, Oct 06, 2021 at 04:08:38PM -0500, Rob Herring wrote: > On Wed, Oct 6, 2021 at 3:44 PM Stafford Horne wrote: > > > > On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote: > > > Replace open coded parsing of CPU nodes' 'reg' property with > > > of_get_cpu_hwid(). > > > > > > Cc: Jonas

[PATCH] Documentation: Fix typo in testing/sysfs-class-cxl

Remove repeated words: "the the lowest" and "this this kernel" Signed-off-by: Sohaib Mohamed --- Documentation/ABI/testing/sysfs-class-cxl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-cx

[PATCH] Documentation: Fix typo in testing/sysfs-class-cxl

Remove repeated worlds: "the the lowest" and "this this kernel" Signed-off-by: Sohaib Mohamed --- Documentation/ABI/testing/sysfs-class-cxl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation/ABI/testing/sysfs-class-c

[PATCH] docs: typo fixes in Documentation/ABI/

All these changes are about to remove repeated words from severals place in the Documentation/ABI/ directory: - In file stable/sysfs-module:41: "the the source" - In file testing/sysfs-bus-rapidio:98: "that that owns" - In file testing/sysfs-class-cxl:106: "the the lowest" - In file testing/sy

[PATCH] docs: typo fixes in Documentation/ABI/

Signed-off-by: Sohaib Mohamed --- Documentation/ABI/stable/sysfs-module | 2 +- Documentation/ABI/testing/sysfs-bus-rapidio | 2 +- Documentation/ABI/testing/sysfs-class-cxl | 4 ++-- Documentation/ABI/testing/sysfs-class-rnbd-client | 2 +

Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()

On Wed, Oct 6, 2021 at 3:44 PM Stafford Horne wrote: > > On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote: > > Replace open coded parsing of CPU nodes' 'reg' property with > > of_get_cpu_hwid(). > > > > Cc: Jonas Bonn > > Cc: Stefan Kristiansson > > Cc: Stafford Horne > > Cc: openr..

Re: [PATCH 06/12] openrisc: Use of_get_cpu_hwid()

On Wed, Oct 06, 2021 at 11:43:26AM -0500, Rob Herring wrote: > Replace open coded parsing of CPU nodes' 'reg' property with > of_get_cpu_hwid(). > > Cc: Jonas Bonn > Cc: Stefan Kristiansson > Cc: Stafford Horne > Cc: openr...@lists.librecores.org > Signed-off-by: Rob Herring > --- > arch/open

Re: [PATCH] perf vendor events power10: Add metric events json file for power10 platform

Kajol, On Wed, Oct 06, 2021 at 01:01:19PM +0530, Kajol Jain wrote: > Add pmu metric json file for power10 platform. Thanks for producing this! A few minor corrections, plus a number of stylistic comments below... > Signed-off-by: Kajol Jain > --- > .../arch/powerpc/power10/metrics.json

[PATCH 12/12] cacheinfo: Set cache 'id' based on DT data

Use the minimum CPU h/w id of the CPUs associated with the cache for the cache 'id'. This will provide a stable id value for a given system. As we need to check all possible CPUs, we can't use the shared_cpu_map which is just online CPUs. As there's not a cache to CPUs mapping in DT, we have to wal

[PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id'

In preparation to set the cache 'id' based on the CPU h/w ids, allow for 64-bit bit 'id' value. The only case that needs this is arm64, so unsigned long is sufficient. Cc: Greg Kroah-Hartman Cc: "Rafael J. Wysocki" Signed-off-by: Rob Herring --- drivers/base/cacheinfo.c | 8 +++- include/

[PATCH 10/12] x86: dt: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Borislav Petkov Cc: x...@kernel.org Cc: "H. Peter Anvin" Signed-off-by: Rob Herring --- arch/x86/kernel/devicetree.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions

[PATCH 09/12] sh: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). Cc: Yoshinori Sato Cc: Rich Felker Cc: linux...@vger.kernel.org Signed-off-by: Rob Herring --- arch/sh/boards/of-generic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/sh/boards/of-

[PATCH 08/12] riscv: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Albert Ou Cc: linux-ri...@lists.infradead.org Signed-off-by: Rob Herring --- arch/riscv/kernel/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/a

[PATCH 07/12] powerpc: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). Cc: Michael Ellerman Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Rob Herring --- arch/powerpc/kernel/smp.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletion

[PATCH 06/12] openrisc: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). Cc: Jonas Bonn Cc: Stefan Kristiansson Cc: Stafford Horne Cc: openr...@lists.librecores.org Signed-off-by: Rob Herring --- arch/openrisc/kernel/smp.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) dif

[PATCH 02/12] ARM: Use of_get_cpu_hwid()

Replace the open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). This change drops an error message for missing 'reg' property, but that should not be necessary as the DT tools will ensure 'reg' is present. Cc: Russell King Signed-off-by: Rob Herring --- arch/arm/kernel/devt

[PATCH 04/12] arm64: Use of_get_cpu_hwid()

Replace the open coded parsing of CPU nodes' 'reg' property with of_get_cpu_hwid(). This change drops an error message for missing 'reg' property, but that should not be necessary as the DT tools will ensure 'reg' is present. Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Rob Herring ---

[PATCH 05/12] csky: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes 'reg' property with of_get_cpu_hwid(). Cc: Guo Ren Cc: linux-c...@vger.kernel.org Signed-off-by: Rob Herring --- arch/csky/kernel/smp.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp

[PATCH 01/12] of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes

There are various open coded implementions parsing the CPU node 'reg' property which contains the CPU's hardware ID. Introduce a new function, of_get_cpu_hwid(), to read the hardware ID. All the callers should be DT only code, so no need for an empty function. Cc: Frank Rowand Signed-off-by: Rob

[PATCH 03/12] ARM: broadcom: Use of_get_cpu_hwid()

Replace open coded parsing of CPU nodes 'reg' property with of_get_cpu_hwid(). Cc: Florian Fainelli Cc: Ray Jui Cc: Scott Branden Cc: bcm-kernel-feedback-l...@broadcom.com Cc: Russell King Signed-off-by: Rob Herring --- arch/arm/mach-bcm/bcm63xx_pmb.c | 6 +++--- 1 file changed, 3 insertions

[PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support

The first 10 patches add a new function, of_get_cpu_hwid(), which parses CPU DT node 'reg' property, and then use it to replace all the open coded versions of parsing CPU node 'reg' properties. The last 2 patches add support for populating the cacheinfo 'id' on DT platforms. The minimum associated

[PATCH v3 4/4] powerpc/perf: Fix data source encodings for L2.1 and L3.1 accesses

Fix the data source encodings to represent L2.1/L3.1(another core's L2/L3 on the same node) accesses properly for power10 and older plaforms. Add new macros(LEVEL/REM) which can be used to add mem_lvl_num and remote field data inside perf_mem_data_src structure. Result in power9 system with patch

[PATCH v3 3/4] tools/perf: Add mem_hops field in perf_mem_data_src structure

Going forward, future generation systems can have more hierarchy within the node/package level but currently we don't have any data source encoding field in perf, which can be used to represent this level of data. Add a new field called 'mem_hops' in the perf_mem_data_src structure which can be us

[PATCH v3 2/4] perf: Add mem_hops field in perf_mem_data_src structure

Going forward, future generation systems can have more hierarchy within the node/package level but currently we don't have any data source encoding field in perf, which can be used to represent this level of data. Add a new field called 'mem_hops' in the perf_mem_data_src structure which can be us

[PATCH v3 1/4] perf: Add comment about current state of PERF_MEM_LVL_* namespace and remove an extra line

Add a comment about PERF_MEM_LVL_* namespace being depricated to some extent in favour of added PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. Remove an extra line present in perf_mem__lvl_scnprintf function. Signed-off-by: Kajol Jain --- include/uapi/linux/perf_event.h | 8 +++- tools/in

[PATCH v3 0/4] Add mem_hops field in perf_mem_data_src structure

Patch set adds a new field called 'mem_hops' in the perf_mem_data_src structure which can be used to represent intra-node/package or inter-node/off-package details. This field is of size 3 bits where PERF_MEM_HOPS_{NA, 0..6} value can be used to present different hop levels data. Patch 1 of the pa

Re: [PATCH] docs: typo fixes in Documentation/ABI/

On Wed, Oct 6, 2021 at 3:21 PM Sohaib Mohamed wrote: > > All these changes are about to remove repeated words from severals place in > the Documentation/ABI/ directory: > > > - In file testing/sysfs-class-rnbd-client:131: "as as the" > > - In file testing/sysfs-class-rtrs-client:81: "the the nam

Re: [PATCH] docs: typo fixes in Documentation/ABI/

On 7/10/21 12:20 am, Sohaib Mohamed wrote: All these changes are about to remove repeated words from severals place in the Documentation/ABI/ directory: - In file stable/sysfs-module:41: "the the source" - In file testing/sysfs-bus-rapidio:98: "that that owns" - In file testing/sysfs-class-cx

Re: [PATCH] docs: typo fixes in Documentation/ABI/

On Wed, Oct 06, 2021 at 03:20:56PM +0200, Sohaib Mohamed wrote: > All these changes are about to remove repeated words from severals place in > the Documentation/ABI/ directory: Please properly line-wrap your changelog text. > - In file stable/sysfs-module:41: "the the source" > > - In file tes

[PATCH v1 03/15] powerpc/kuap: Add a generic intermediate layer

Make the following functions generic to all platforms. - bad_kuap_fault() - kuap_assert_locked() - kuap_save_and_lock() (PPC32 only) - kuap_kernel_restore() - kuap_get_and_assert_locked() And for all platforms except book3s/64 - allow_user_access() - prevent_user_access() - prevent_user_access_ret

[PATCH v1 02/15] powerpc/32s: Save content of sr0 to avoid 'mfsr'

Calling 'mfsr' to get the content of segment registers is heavy, in addition it requires clearing of the 'reserved' bits. In order to avoid this operation, save it in mm context and in thread struct. The saved sr0 is the one used by kernel, this means that on locking entry it can be used as is.

[PATCH v1 04/15] powerpc/kuap: Check KUAP activation in generic functions

Today, every platform checks that KUAP is not de-activated before doing the real job. Move the verification out of platform specific functions. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/kup.h | 34 +++- arch/powerpc/include/asm/book3s/64/kup.h |

[PATCH v1 05/15] powerpc/kuap: Remove __kuap_assert_locked()

__kuap_assert_locked() is redundant with __kuap_get_and_assert_locked(). Move the verification of CONFIG_PPC_KUAP_DEBUG in kuap_assert_locked() and make it call __kuap_get_and_assert_locked() directly. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/kup.h | 5 - a

[PATCH v1 08/15] powerpc/config: Add CONFIG_BOOKE_OR_40x

We have many functionnalities common to 40x and BOOKE, it leads to many places with #if defined(CONFIG_BOOKE) || defined(CONFIG_40x). We are going to add a few more with KUAP for booke/40x, so create a new symbol which is defined when either BOOKE or 40x is defined. Signed-off-by: Christophe Lero

[PATCH v1 06/15] powerpc/kuap: Add kuap_lock()

Add kuap_lock() and call it when entering interrupts from user. It is called kuap_lock() as it is similar to kuap_save_and_lock() without the save. However book3s/32 already have a kuap_lock(). Rename it kuap_lock_addr(). Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/k

[PATCH v1 11/15] powerpc/kuap: Wire-up KUAP on 44x

This adds KUAP support to 44x. This is done by checking the content of SPRN_PID at the time it is read and written into SPRN_MMUCR. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_44x.S | 16 arch/powerpc/platforms/Kconfig.cputype | 1 + 2 files changed, 17

[PATCH v1 15/15] powerpc: Remove CONFIG_PPC_HAVE_KUAP

All platforms now have KUAP so remove CONFIG_PPC_HAVE_KUAP Signed-off-by: Christophe Leroy --- arch/powerpc/mm/nohash/kup.c | 1 - arch/powerpc/platforms/Kconfig.cputype | 11 --- 2 files changed, 12 deletions(-) diff --git a/arch/powerpc/mm/nohash/kup.c b/arch/powerpc/mm/noh

[PATCH v1 14/15] powerpc/kuap: Wire-up KUAP on book3e/64

This adds KUAP support to book3e/64. This is done by reading the content of SPRN_MAS1 and checking the TID at the time user pgtable is loaded. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/nohash/tlb_low_64e.S | 40 ++ arch/powerpc/platforms/Kconfig.cputype | 1 +

[PATCH v1 09/15] powerpc/kuap: Prepare for supporting KUAP on BOOK3E/64

Also call kuap_lock() and kuap_save_and_lock() from interrupt functions with CONFIG_PPC64. For book3s/64 we keep them empty as it is done in assembly. Also do the locked assert when switching task unless it is book3s/64. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/64/ku

[PATCH v1 00/15] powerpc: Add KUAP support for BOOKE and 40x

On booke/40x we don't have segments like book3s/32. On booke/40x we don't have access protection groups like 8xx. Use the PID register to provide user access protection. Kernel address space can be accessed with any PID. User address space has to be accessed with the PID of the user. User PID is a

[PATCH v1 13/15] powerpc/kuap: Wire-up KUAP on 85xx in 32 bits mode.

This adds KUAP support to 85xx in 32 bits mode. This is done by reading the content of SPRN_MAS1 and checking the TID at the time user pgtable is loaded. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_fsl_booke.S | 12 arch/powerpc/platforms/Kconfig.cputype | 1 + 2

[PATCH v1 12/15] powerpc/kuap: Wire-up KUAP on 40x

This adds KUAP support to 40x. This is done by checking the content of SPRN_PID at the time user pgtable is loaded. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_40x.S | 8 arch/powerpc/platforms/Kconfig.cputype | 1 + 2 files changed, 9 insertions(+) diff --git

[PATCH v1 07/15] powerpc/nohash: Move setup_kuap out of 8xx.c

In order to reuse it on booke/4xx, move KUAP setup routine out of 8xx.c Make them usable on SMP by removing the __init tag as it is called for each CPU. And use __prevent_user_access() instead of hard coding initial lock. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/nohash/8xx.c| 21

[PATCH v1 01/15] powerpc/32s: Do kuep_lock() and kuep_unlock() in assembly

When interrupt and syscall entries where converted to C, KUEP locking and unlocking was also converted. It improved performance by unrolling the loop, and allowed easily implementing boot time deactivation of KUEP. However, null_syscall selftest shows that KUEP is still heavy (361 cycles with KUEP

[PATCH v1 10/15] powerpc: Add KUAP support for BOOKE and 40x

On booke/40x we don't have segments like book3s/32. On booke/40x we don't have access protection groups like 8xx. Use the PID register to provide user access protection. Kernel address space can be accessed with any PID. User address space has to be accessed with the PID of the user. User PID is a

Re: [PATCH] docs: typo fixes in Documentation/ABI/

On Wed, Oct 06, 2021 at 02:13:25PM +0200, Sohaib Mohamed wrote: > Signed-off-by: Sohaib Mohamed I can not take patches without any changelog text, sorry. thanks, greg k-h

Re: [PATCH] docs: typo fixes in Documentation/ABI/

Em Wed, 6 Oct 2021 14:13:25 +0200 Sohaib Mohamed escreveu: > Signed-off-by: Sohaib Mohamed Please add a description for the patch, explaining what typo issues you fixed. The patch itself looks sane to me. > --- > Documentation/ABI/stable/sysfs-module | 2 +- > Documentat

Re: [PATCH] KVM: PPC: Defer vtime accounting 'til after IRQ handling

On Wed, 6 Oct 2021 09:37:45 +0200 Laurent Vivier wrote: > Commit 61bd0f66ff92 has moved guest_enter() out of the interrupt > protected area to be able to have updated tick counters, but > commit 112665286d08 moved back to this area to avoid wrong > context warning (or worse). > > None of them a

[PATCH] KVM: PPC: Defer vtime accounting 'til after IRQ handling

Commit 61bd0f66ff92 has moved guest_enter() out of the interrupt protected area to be able to have updated tick counters, but commit 112665286d08 moved back to this area to avoid wrong context warning (or worse). None of them are correct, to fix the problem port to POWER the x86 fix 160457140187 (

[PATCH] perf vendor events power10: Add metric events json file for power10 platform

Add pmu metric json file for power10 platform. Signed-off-by: Kajol Jain --- .../arch/powerpc/power10/metrics.json | 772 ++ 1 file changed, 772 insertions(+) create mode 100644 tools/perf/pmu-events/arch/powerpc/power10/metrics.json diff --git a/tools/perf/pmu-events/a