On Mon, Jun 14, 2021 at 08:28:01AM +0200, Christoph Hellwig wrote:
> I think merging this with the next two patches would be a little more
> clear.
Sorry, I mean the next patch and the previous one.
I think merging this with the next two patches would be a little more
clear.
On Fri, Jun 11, 2021 at 11:26:54PM +0800, Claire Chang wrote:
> Add a new function, release_slots, to make the code reusable for supporting
> different bounce buffer pools, e.g. restricted DMA pool.
>
> Signed-off-by: Claire Chang
> ---
> kernel/dma/swiotlb.c | 35 ---
On Fri, Jun 11, 2021 at 11:26:53PM +0800, Claire Chang wrote:
> Move the maintenance of alloc_size to find_slots for better code
> reusability later.
Looks good,
Reviewed-by: Christoph Hellwig
On Fri, Jun 11, 2021 at 11:26:52PM +0800, Claire Chang wrote:
> Regardless of swiotlb setting, the restricted DMA pool is preferred if
> available.
>
> The restricted DMA pools provide a basic level of protection against the
> DMA overwriting buffer contents at unexpected times. However, to protec
> kernel/dma/direct.c | 2 +-
> kernel/dma/swiotlb.c | 4 ++--
> 6 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
> b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
> index ce6b664b10aa..
Looks good,
Reviewed-by: Christoph Hellwig
On Fri, Jun 11, 2021 at 11:26:49PM +0800, Claire Chang wrote:
> Add the initialization function to create restricted DMA pools from
> matching reserved-memory nodes.
Bisection hazard: we should only add the new config option when the
code is actually read to be used. So this patch should move to
On Fri, Jun 11, 2021 at 11:33:15PM +0800, Claire Chang wrote:
> I'm not sure if this would break arch/x86/pci/sta2x11-fixup.c
> swiotlb_late_init_with_default_size is called here
> https://elixir.bootlin.com/linux/v5.13-rc5/source/arch/x86/pci/sta2x11-fixup.c#L60
It will. It will also break all n
On Fri, Jun 11, 2021 at 11:26:47PM +0800, Claire Chang wrote:
> Split the debugfs creation to make the code reusable for supporting
> different bounce buffer pools, e.g. restricted DMA pool.
>
> Signed-off-by: Claire Chang
> ---
> kernel/dma/swiotlb.c | 23 ---
> 1 file chang
On Fri, Jun 11, 2021 at 11:26:46PM +0800, Claire Chang wrote:
> + spin_lock_init(&mem->lock);
> + for (i = 0; i < mem->nslabs; i++) {
> + mem->slots[i].list = IO_TLB_SEGSIZE - io_tlb_offset(i);
> + mem->slots[i].orig_addr = INVALID_PHYS_ADDR;
> + mem->slo
Excerpts from Christophe Leroy's message of June 14, 2021 3:31 pm:
>
>
> Le 14/06/2021 à 03:29, Nicholas Piggin a écrit :
>> Excerpts from Nicholas Piggin's message of June 14, 2021 10:47 am:
>>> Excerpts from Michael Ellerman's message of June 8, 2021 11:46 pm:
In commit 96d7a4e06fab ("powe
Excerpts from Christophe Leroy's message of June 14, 2021 3:30 pm:
>
>
> Le 14/06/2021 à 03:32, Nicholas Piggin a écrit :
>> Excerpts from Michael Ellerman's message of June 10, 2021 5:29 pm:
>>> When delivering a signal to a sigaction style handler (SA_SIGINFO), we
>>> pass pointers to the sigin
Le 14/06/2021 à 03:29, Nicholas Piggin a écrit :
Excerpts from Nicholas Piggin's message of June 14, 2021 10:47 am:
Excerpts from Michael Ellerman's message of June 8, 2021 11:46 pm:
In commit 96d7a4e06fab ("powerpc/signal64: Rewrite handle_rt_signal64()
to minimise uaccess switches") the 64
Le 14/06/2021 à 03:32, Nicholas Piggin a écrit :
Excerpts from Michael Ellerman's message of June 10, 2021 5:29 pm:
When delivering a signal to a sigaction style handler (SA_SIGINFO), we
pass pointers to the siginfo and ucontext via r4 and r5.
Currently we populate the values in those regist
Le 13/06/2021 à 13:13, Aneesh Kumar K.V a écrit :
On 6/13/21 4:20 PM, Matthew Wilcox wrote:
On Sun, Jun 13, 2021 at 02:36:13PM +0530, Aneesh Kumar K.V wrote:
IIUC the reason why we do have pmd_pgtable() is that pgtable_t type
is arch dependent. On some architecture it is pte_t * and on the o
Performance monitoring support for papr-scm nvdimm devices
via perf interface is added which includes addition of pmu
functions like add/del/read/event_init for nvdimm_pmu struture.
A new parameter 'priv' in added to the pdev_archdata structure to save
nvdimm_pmu device pointer, to handle the unre
Patchset adds performance stats reporting support for nvdimm.
Added interface includes support for pmu register/unregister
functions. A structure is added called nvdimm_pmu to be used for
adding arch/platform specific data such as supported events, cpumask
pmu event functions like event_init/add/re
Details is added for the event, cpumask and format attributes
in the ABI documentation.
Signed-off-by: Kajol Jain
---
Documentation/ABI/testing/sysfs-bus-papr-pmem | 31 +++
1 file changed, 31 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-papr-pmem
b/Documentat
A common interface is added to get performance stats reporting
support for nvdimm devices. Added interface includes support for
pmu register/unregister functions, cpu hotplug and pmu event
functions like event_init/add/read/del.
User could use the standard perf tool to access perf
events exposed vi
A structure is added, called nvdimm_pmu, for performance
stats reporting support of nvdimm devices. It can be used to add
nvdimm pmu data such as supported events and pmu event functions
like event_init/add/read/del with cpu hotplug support.
Signed-off-by: Kajol Jain
---
include/linux/nd.h | 43
Excerpts from Nicholas Piggin's message of June 14, 2021 2:47 pm:
> Excerpts from Nicholas Piggin's message of June 14, 2021 2:14 pm:
>> Excerpts from Andy Lutomirski's message of June 14, 2021 1:52 pm:
>>> On 6/13/21 5:45 PM, Nicholas Piggin wrote:
Excerpts from Andy Lutomirski's message of J
Excerpts from Nicholas Piggin's message of June 14, 2021 2:14 pm:
> Excerpts from Andy Lutomirski's message of June 14, 2021 1:52 pm:
>> On 6/13/21 5:45 PM, Nicholas Piggin wrote:
>>> Excerpts from Andy Lutomirski's message of June 9, 2021 2:20 am:
On 6/4/21 6:42 PM, Nicholas Piggin wrote:
>>>
Excerpts from Andy Lutomirski's message of June 14, 2021 1:52 pm:
> On 6/13/21 5:45 PM, Nicholas Piggin wrote:
>> Excerpts from Andy Lutomirski's message of June 9, 2021 2:20 am:
>>> On 6/4/21 6:42 PM, Nicholas Piggin wrote:
Add CONFIG_MMU_TLB_REFCOUNT which enables refcounting of the lazy tlb
On 6/13/21 5:45 PM, Nicholas Piggin wrote:
> Excerpts from Andy Lutomirski's message of June 9, 2021 2:20 am:
>> On 6/4/21 6:42 PM, Nicholas Piggin wrote:
>>> Add CONFIG_MMU_TLB_REFCOUNT which enables refcounting of the lazy tlb mm
>>> when it is context switched. This can be disabled by architectu
Excerpts from Haren Myneni's message of June 13, 2021 9:05 pm:
>
> Changes to export the following NXGZIP capabilities through sysfs:
>
> /sys/devices/vio/ibm,compression-v1/nx_gzip_caps:
> min_compress_len /*Recommended minimum compress length in bytes*/
> min_decompress_len /*Recommended minim
Excerpts from Haren Myneni's message of June 13, 2021 9:04 pm:
>
> The hypervisor provides different capabilities that it supports
> to define the user space NX request. These capabilities are
> recommended minimum compression / decompression lengths and the
> maximum request buffer size in bytes.
Excerpts from Haren Myneni's message of June 13, 2021 9:04 pm:
>
> The user space uses /dev/crypto/nx-gzip interface to setup VAS
> windows, create paste mapping and close windows. This patch adds
> changes to create/remove this interface with VAS register/unregister
> functions on PowerVM platfor
Excerpts from Haren Myneni's message of June 13, 2021 8:58 pm:
>
> If a coprocessor encounters an error translating an address, the
> VAS will cause an interrupt in the host. The kernel processes
> the fault by updating CSB. This functionality is same for both
> powerNV and pseries. So this patch
Excerpts from Haren Myneni's message of June 13, 2021 9:03 pm:
>
> Rename nx-842-pseries.c to nx-common-pseries.c to add code for new
> GZIP compression type. The actual functionality is not changed in
> this patch.
>
> Signed-off-by: Haren Myneni
> Acked-by: Herbert Xu
Acked-by: Nicholas Pigg
Excerpts from Haren Myneni's message of June 13, 2021 9:02 pm:
>
> NX generates an interrupt when sees a fault on the user space
> buffer and the hypervisor forwards that interrupt to OS. Then
> the kernel handles the interrupt by issuing H_GET_NX_FAULT hcall
> to retrieve the fault CRB informatio
Excerpts from Haren Myneni's message of June 13, 2021 9:02 pm:
>
> This patch adds VAS window allocatioa/close with the corresponding
> hcalls. Also changes to integrate with the existing user space VAS
> API and provide register/unregister functions to NX pseries driver.
>
> The driver register
Excerpts from Haren Myneni's message of June 13, 2021 9:01 pm:
>
> The hypervisor provides VAS capabilities for GZIP default and QoS
> features. These capabilities gives information for the specific
> features such as total number of credits available in LPAR,
> maximum credits allowed per window,
Excerpts from Haren Myneni's message of June 13, 2021 9:00 pm:
>
> PowerVM introduces two different type of credits: Default and Quality
> of service (QoS).
>
> The total number of default credits available on each LPAR depends
> on CPU resources configured. But these credits can be shared or
> o
Excerpts from Haren Myneni's message of June 13, 2021 8:59 pm:
>
> This patch adds hcalls and other definitions. Also define structs
> that are used in VAS implementation on PowerVM.
>
> Signed-off-by: Haren Myneni
I haven't got the specs to verify it against, but previous comments on
naming e
Excerpts from Haren Myneni's message of June 13, 2021 8:58 pm:
>
> Many elements in vas_struct are used on PowerNV and PowerVM
> platforms. vas_window is used for both TX and RX windows on
> PowerNV and for TX windows on PowerVM. So some elements are
> specific to these platforms.
>
> So this pat
Excerpts from Haren Myneni's message of June 13, 2021 8:57 pm:
>
> Take pid and mm references when each window opens and drops during
> close. This functionality is needed for powerNV and pseries. So
> this patch defines the existing code as functions in common book3s
> platform vas-api.c
>
> Sig
Excerpts from Haren Myneni's message of June 13, 2021 8:57 pm:
>
> PowerNV uses registers to open/close VAS windows, and getting the
> paste address. Whereas the hypervisor calls are used on PowerVM.
>
> This patch adds the platform specific user space window operations
> and register with the co
Excerpts from Haren Myneni's message of June 13, 2021 8:54 pm:
>
> The kernel handles the NX fault by updating CSB or sending
> signal to process. In multithread applications, children can
> open VAS windows and can exit without closing them. But the
> parent can continue to send NX requests with
Excerpts from Haren Myneni's message of June 13, 2021 8:55 pm:
>
> Using the same /dev/crypto/nx-gzip interface for both powerNV and
> pseries. So this patch creates platforms/book3s/ and moves VAS API
> to that directory. The actual functionality is not changed.
>
> Signed-off-by: Haren Myneni
Excerpts from Michael Ellerman's message of June 10, 2021 5:29 pm:
> When delivering a signal to a sigaction style handler (SA_SIGINFO), we
> pass pointers to the siginfo and ucontext via r4 and r5.
>
> Currently we populate the values in those registers by reading the
> pointers out of the sigfra
Excerpts from Nicholas Piggin's message of June 14, 2021 10:47 am:
> Excerpts from Michael Ellerman's message of June 8, 2021 11:46 pm:
>> In commit 96d7a4e06fab ("powerpc/signal64: Rewrite handle_rt_signal64()
>> to minimise uaccess switches") the 64-bit signal code was rearranged to
>> use user_w
Excerpts from Michael Ellerman's message of June 8, 2021 11:46 pm:
> In commit 96d7a4e06fab ("powerpc/signal64: Rewrite handle_rt_signal64()
> to minimise uaccess switches") the 64-bit signal code was rearranged to
> use user_write_access_begin/end().
>
> As part of that change the call to copy_si
Excerpts from Andy Lutomirski's message of June 9, 2021 2:20 am:
> On 6/4/21 6:42 PM, Nicholas Piggin wrote:
>> Add CONFIG_MMU_TLB_REFCOUNT which enables refcounting of the lazy tlb mm
>> when it is context switched. This can be disabled by architectures that
>> don't require this refcounting if th
On Sun, Jun 13, 2021 at 2:06 AM Aneesh Kumar K.V
wrote:
>
> IIUC the reason why we do have pmd_pgtable() is that pgtable_t type
> is arch dependent. On some architecture it is pte_t * and on the other
> struct page *. The reason being highmem and level 4 page table can
> be located in highmem.
Ho
On Fri, Jun 11, 2021 at 4:32 AM Yang Yingliang wrote:
> rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo");
> tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo");
> + if (!rx_res || !tx_res) {
> + dev_err(dev, "Invalid resou
On 6/13/21 4:20 PM, Matthew Wilcox wrote:
On Sun, Jun 13, 2021 at 02:36:13PM +0530, Aneesh Kumar K.V wrote:
IIUC the reason why we do have pmd_pgtable() is that pgtable_t type
is arch dependent. On some architecture it is pte_t * and on the other
struct page *. The reason being highmem and level
Changes to export the following NXGZIP capabilities through sysfs:
/sys/devices/vio/ibm,compression-v1/nx_gzip_caps:
min_compress_len /*Recommended minimum compress length in bytes*/
min_decompress_len /*Recommended minimum decompress length in bytes*/
req_max_processed_len /* Maximum number of
The hypervisor provides different capabilities that it supports
to define the user space NX request. These capabilities are
recommended minimum compression / decompression lengths and the
maximum request buffer size in bytes.
Changes to get NX overall capabilities which points to the
specific fe
The user space uses /dev/crypto/nx-gzip interface to setup VAS
windows, create paste mapping and close windows. This patch adds
changes to create/remove this interface with VAS register/unregister
functions on PowerVM platform.
Signed-off-by: Haren Myneni
Acked-by: Herbert Xu
---
drivers/cryp
Rename nx-842-pseries.c to nx-common-pseries.c to add code for new
GZIP compression type. The actual functionality is not changed in
this patch.
Signed-off-by: Haren Myneni
Acked-by: Herbert Xu
---
drivers/crypto/nx/Makefile | 2 +-
drivers/crypto/nx/{nx-842-p
NX generates an interrupt when sees a fault on the user space
buffer and the hypervisor forwards that interrupt to OS. Then
the kernel handles the interrupt by issuing H_GET_NX_FAULT hcall
to retrieve the fault CRB information.
This patch also adds changes to setup and free IRQ per each
window a
This patch adds VAS window allocatioa/close with the corresponding
hcalls. Also changes to integrate with the existing user space VAS
API and provide register/unregister functions to NX pseries driver.
The driver register function is used to create the user space
interface (/dev/crypto/nx-gzip)
The hypervisor provides VAS capabilities for GZIP default and QoS
features. These capabilities gives information for the specific
features such as total number of credits available in LPAR,
maximum credits allowed per window, maximum credits allowed in
LPAR, whether usermode copy/paste is support
This patch adds the following hcall wrapper functions to allocate,
modify and deallocate VAS windows, and retrieve VAS capabilities.
H_ALLOCATE_VAS_WINDOW: Allocate VAS window
H_DEALLOCATE_VAS_WINDOW: Close VAS window
H_MODIFY_VAS_WINDOW: Setup window before using
H_QUERY_VAS_CAPABILITIES: Get V
PowerVM introduces two different type of credits: Default and Quality
of service (QoS).
The total number of default credits available on each LPAR depends
on CPU resources configured. But these credits can be shared or
over-committed across LPARs in shared mode which can result in
paste command
This patch adds hcalls and other definitions. Also define structs
that are used in VAS implementation on PowerVM.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/hvcall.h| 7 ++
arch/powerpc/include/asm/vas.h | 30 +++
arch/powerpc/platforms/pseries/vas.h | 125 ++
Many elements in vas_struct are used on PowerNV and PowerVM
platforms. vas_window is used for both TX and RX windows on
PowerNV and for TX windows on PowerVM. So some elements are
specific to these platforms.
So this patch defines common vas_window and platform
specific window structs (pnv_vas_w
If a coprocessor encounters an error translating an address, the
VAS will cause an interrupt in the host. The kernel processes
the fault by updating CSB. This functionality is same for both
powerNV and pseries. So this patch moves these functions to
common vas-api.c and the actual functionality i
Take pid and mm references when each window opens and drops during
close. This functionality is needed for powerNV and pseries. So
this patch defines the existing code as functions in common book3s
platform vas-api.c
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/vas.h |
PowerNV uses registers to open/close VAS windows, and getting the
paste address. Whereas the hypervisor calls are used on PowerVM.
This patch adds the platform specific user space window operations
and register with the common VAS user space interface.
Signed-off-by: Haren Myneni
---
arch/pow
powerNV and pseries drivers register / unregister to the corresponding
platform specific VAS separately. Then these VAS functions call the
common API with the specific window operations. So rename powerNV VAS
API register/unregister functions.
Signed-off-by: Haren Myneni
Reviewed-by: Nicholas P
Using the same /dev/crypto/nx-gzip interface for both powerNV and
pseries. So this patch creates platforms/book3s/ and moves VAS API
to that directory. The actual functionality is not changed.
Signed-off-by: Haren Myneni
---
arch/powerpc/platforms/Kconfig| 1 +
arch/powerp
The kernel handles the NX fault by updating CSB or sending
signal to process. In multithread applications, children can
open VAS windows and can exit without closing them. But the
parent can continue to send NX requests with these windows. To
prevent pid reuse, reference will be taken on pid and
Virtual Accelerator Switchboard (VAS) allows kernel subsystems
and user space processes to directly access the Nest Accelerator
(NX) engines which provides HW compression. The true user mode
VAS/NX support on PowerNV is already included in Linux. Whereas
PowerVM support is available from P10 onwa
On Sun, Jun 13, 2021 at 02:36:13PM +0530, Aneesh Kumar K.V wrote:
> IIUC the reason why we do have pmd_pgtable() is that pgtable_t type
> is arch dependent. On some architecture it is pte_t * and on the other
> struct page *. The reason being highmem and level 4 page table can
> be located in highm
Linus Torvalds writes:
> On Thu, Jun 10, 2021 at 1:36 AM Aneesh Kumar K.V
> wrote:
>>
>> @@ -306,8 +306,7 @@ static bool move_normal_pud(struct vm_area_struct *vma,
>> unsigned long old_addr,
>>
>> VM_BUG_ON(!pud_none(*new_pud));
>>
>> - /* Set the new pud */
>> - set_pud_at
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