On Tue, Feb 02, 2021 at 11:17:30AM +0800, Yang Li wrote:
> Eliminate the following coccicheck warning:
> ./arch/powerpc/crypto/sha256-spe-glue.c:132:2-3: Unneeded
> semicolon
>
> Reported-by: Abaci Robot
> Signed-off-by: Yang Li
> ---
> arch/powerpc/crypto/sha256-spe-glue.c | 2 +-
> 1 file cha
On Thu, Feb 04, 2021 at 11:09:40AM +, Lee Jones wrote:
> This set is part of a larger effort attempting to clean-up W=1
> kernel builds, which are currently overwhelmingly riddled with
> niggly little warnings.
>
> This is set 1 of 2 sets required to fully clean Crypto.
>
> Lee Jones (20):
>
-20210209
x86_64 randconfig-a001-20210209
x86_64 randconfig-a005-20210209
x86_64 randconfig-a004-20210209
x86_64 randconfig-a002-20210209
x86_64 randconfig-a003-20210209
i386 randconfig-a001-20210209
i386
rror:no-previous-prototype-for-exit_lazy_flush_tlb
|-- powerpc-ppc64_defconfig
| `--
arch-powerpc-mm-book3s64-radix_tlb.c:error:no-previous-prototype-for-exit_lazy_flush_tlb
`-- powerpc64-randconfig-r036-20210209
`--
arch-powerpc-platforms-amigaone-setup.c:error:no-previous-prototype-for-amiga
allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210209
x86_64 randconfig-a001
onfig
i386defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210
The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
perf event to count L1D misses. The value of this event has changed
over time:
- Power7 uses 0x400f0
- Power8 and Power9 use both 0x400f0 and 0x3e054
- Power10 uses only 0x3e054
Update these selftests to use the value 0x3e05
> Differentiate between hardware not supporting hugepages and user disabling THP
> via 'echo never > /sys/kernel/mm/transparent_hugepage/enabled'
>
> For the devdax namespace, the kernel handles the above via the
> supported_alignment attribute and failing to initialize the namespace
> if the names
On Sun Feb 7, 2021 at 10:44 PM CST, Daniel Axtens wrote:
> Hi Chris,
>
> These two paragraphs are a little confusing and they seem slightly
> repetitive. But I get the general idea. Two specific comments below:
Umm... yeah only one of those was supposed to be sent. I will reword
this for the next
On Tue Feb 9, 2021 at 3:45 PM CST, Christophe Leroy wrote:
> "Christopher M. Riedl" a écrit :
>
> > Usually sigset_t is exactly 8B which is a "trivial" size and does not
> > warrant using __copy_from_user(). Use __get_user() directly in
> > anticipation of future work to remove the trivial size op
Excerpts from Paul Mackerras's message of February 10, 2021 11:28 am:
> On Mon, Jan 18, 2021 at 04:28:07PM +1000, Nicholas Piggin wrote:
>> The slbmte instruction is legal in radix mode, including radix guest
>> mode. This means radix guests can load the SLB with arbitrary data.
>>
>> KVM host doe
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
next-test
head: 5811244192fc4e18c001c69300044c2acf30bd91
commit: 053d58c870298d62b9c5154672ef2f1684c4ea43 [68/159] powerpc/amigaone:
Move PHB discovery
config: powerpc64-randconfig-r036-20210209 (attached as .config
Excerpts from Christophe Leroy's message of February 10, 2021 3:03 am:
>
>
> Le 09/02/2021 à 15:31, David Laight a écrit :
>> From: Segher Boessenkool
>>> Sent: 09 February 2021 13:51
>>>
>>> On Tue, Feb 09, 2021 at 12:36:20PM +1000, Nicholas Piggin wrote:
What if you did this?
>>>
+sta
Excerpts from Christophe Leroy's message of February 10, 2021 12:31 am:
>
>
> Le 09/02/2021 à 03:02, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of February 9, 2021 1:10 am:
>>> For book3s/64, FULL_REGS() is 'true' at all time, so the test voids.
>>> For others, non vola
Excerpts from Christophe Leroy's message of February 10, 2021 2:13 am:
>
>
> Le 09/02/2021 à 02:55, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of February 9, 2021 1:10 am:
>>> When r3 is not modified, reload it from regs->orig_r3 to free
>>> volatile registers. This avo
On Mon, Jan 18, 2021 at 04:28:07PM +1000, Nicholas Piggin wrote:
> The slbmte instruction is legal in radix mode, including radix guest
> mode. This means radix guests can load the SLB with arbitrary data.
>
> KVM host does not clear the SLB when exiting a guest if it was a
> radix guest, which wo
On Tue, Feb 09, 2021 at 10:26:21AM +, Christophe Leroy wrote:
> get_tbl() is confusing as it returns the content TBL register
> on PPC32 but the concatenation of TBL and TBU on PPC64.
>
> Use mftb() instead.
>
> This will allow the removal of get_tbl() in a following patch.
Acked-by: Mark Br
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
next-test
head: 5811244192fc4e18c001c69300044c2acf30bd91
commit: 83f84041ff1cf6c23fc38861218af2d4ca2d9b38 [67/159] powerpc/83xx: Move
PHB discovery
config: powerpc-kmeter1_defconfig (attached as .config)
compiler: powerpc
"Christopher M. Riedl" a écrit :
Usually sigset_t is exactly 8B which is a "trivial" size and does not
warrant using __copy_from_user(). Use __get_user() directly in
anticipation of future work to remove the trivial size optimizations
from __copy_from_user(). Calling __get_user() also results i
-20210209 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
c9439ca36342fb6013187d0a69aef92736951476)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x
Only book3s/64 has scv. No need to check the 0x7ff0 trap on 32 or 64e.
For that, add a helper trap_is_unsupported_scv() similar to
trap_is_scv().
And ignore the scv parameter in syscall_exit_prepare (Save 14 cycles
346 => 332 cycles)
Signed-off-by: Christophe Leroy
---
v5: Added a helper trap_is
The handling of SPRN_DBCR0 and other registers can easily
be done in C instead of ASM.
For that, create booke_load_dbcr0() and booke_restore_dbcr0().
Signed-off-by: Christophe Leroy
---
v5: New
v6: Refactor into helpers
---
arch/powerpc/include/asm/interrupt.h | 12
arch/powerpc/includ
This series implements C syscall entry/exit for PPC32. It reuses
the work already done for PPC64.
This series is based on today's next-test (f538b53fd47a) where main patchs from
v5 are merged in.
The first patch is important for performance.
v6:
- Forced scv param to 0 on syscall_exit_prepare()
Update CONFIG_KEXEC_FILE to select CONFIG_HAVE_IMA_KEXEC, if CONFIG_IMA
is enabled, to indicate that the IMA measurement log information is
present in the device tree for ARM64.
Co-developed-by: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
Signed-off-by: Lakshmi Ramasubramanian
Suggeste
delete_fdt_mem_rsv() defined in "arch/powerpc/kexec/file_load.c"
has been renamed to fdt_find_and_del_mem_rsv(), and moved to
"drivers/of/kexec.c".
Remove delete_fdt_mem_rsv() in "arch/powerpc/kexec/file_load.c".
Co-developed-by: Prakhar Srivastava
Signed-off-by: Prakhar Srivastava
Signed-off-b
fdt_appendprop_addrrange() function adds a property, with the given name,
to the device tree at the given node offset, and also sets the address
and size of the property. This function should be used to add
"linux,ima-kexec-buffer" property to the device tree and set the address
and size of the IM
The functions defined in "arch/powerpc/kexec/ima.c" handle setting up
and freeing the resources required to carry over the IMA measurement
list from the current kernel to the next kernel across kexec system call.
These functions do not have architecture specific code, but are
currently limited to p
CONFIG_HAVE_IMA_KEXEC is enabled to indicate that the IMA measurement
log information is present in the device tree. This should be selected
only if CONFIG_IMA is enabled.
Update CONFIG_KEXEC_FILE to select CONFIG_HAVE_IMA_KEXEC, if CONFIG_IMA
is enabled, to indicate that the IMA measurement log i
The fields ima_buffer_addr and ima_buffer_size in "struct kimage_arch"
for powerpc are used to carry forward the IMA measurement list across
kexec system call. These fields are not architecture specific, but are
currently limited to powerpc.
arch_ima_add_kexec_buffer() defined in "arch/powerpc/ke
From: Rob Herring
The code for setting up the /chosen node in the device tree
and updating the memory reservation for the next kernel has been
moved to of_kexec_alloc_and_setup_fdt() defined in "drivers/of/kexec.c".
Use the common of_kexec_alloc_and_setup_fdt() to setup the device tree
and updat
From: Rob Herring
The code for setting up the /chosen node in the device tree
and updating the memory reservation for the next kernel has been
moved to of_kexec_alloc_and_setup_fdt() defined in "drivers/of/kexec.c".
Use the common of_kexec_alloc_and_setup_fdt() to setup the device tree
and updat
From: Rob Herring
The architecture specific field, elfcorehdr_addr in struct kimage_arch,
that holds the address of the buffer in memory for ELF core header for
powerpc has a different name than the one used for arm64. This makes
it hard to have a common code for setting up the device tree for
k
From: Rob Herring
Both arm64 and powerpc do essentially the same FDT /chosen setup for
kexec. The differences are either omissions that arm64 should have
or additional properties that will be ignored. The setup code can be
combined and shared by both powerpc and arm64.
The differences relative
On kexec file load Integrity Measurement Architecture (IMA) subsystem
may verify the IMA signature of the kernel and initramfs, and measure
it. The command line parameters passed to the kernel in the kexec call
may also be measured by IMA. A remote attestation service can verify
a TPM quote based
From: Christophe Leroy
> Sent: 09 February 2021 17:04
>
> Le 09/02/2021 à 15:31, David Laight a écrit :
> > From: Segher Boessenkool
> >> Sent: 09 February 2021 13:51
> >>
> >> On Tue, Feb 09, 2021 at 12:36:20PM +1000, Nicholas Piggin wrote:
> >>> What if you did this?
> >>
> >>> +static inline s
Le 09/02/2021 à 15:31, David Laight a écrit :
From: Segher Boessenkool
Sent: 09 February 2021 13:51
On Tue, Feb 09, 2021 at 12:36:20PM +1000, Nicholas Piggin wrote:
What if you did this?
+static inline struct task_struct *get_current(void)
+{
+ register struct task_struct *task asm
The IPI interrupt has its own domain now. Testing the HW interrupt
number is not needed anymore.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/common.c
b/arch/powerpc/sysdev/xi
Now that the IPI interrupt has its own domain, the checks on the HW
interrupt number XIVE_IPI_HW_IRQ and on the chip can be replaced by a
check on the domain.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c | 18 --
1 file changed, 4 insertions(+), 14 deleti
The 'chip_id' field of the XIVE CPU structure is used to choose a
target for a source located on the same chip when possible. This field
is assigned on the PowerNV platform using the "ibm,chip-id" property
on pSeries under KVM when NUMA nodes are defined but it is undefined
under PowerVM. The XIVE
ipistorm [*] can be used to benchmark the raw interrupt rate of an
interrupt controller by measuring the number of IPIs a system can
sustain. When applied to the XIVE interrupt controller of POWER9 and
POWER10 systems, a significant drop of the interrupt rate can be
observed when crossing the secon
Hello,
ipistorm [*] can be used to benchmark the raw interrupt rate of an
interrupt controller by measuring the number of IPIs a system can
sustain. When applied to the XIVE interrupt controller of POWER9 and
POWER10 systems, a significant drop of the interrupt rate can be
observed when crossing t
The IPI interrupt is a special case of the XIVE IRQ domain. When
mapping and unmapping the interrupts in the Linux interrupt number
space, the HW interrupt number 0 (XIVE_IPI_HW_IRQ) is checked to
distinguish the IPI interrupt from other interrupts of the system.
Simplify the XIVE interrupt domain
Le 09/02/2021 à 02:55, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of February 9, 2021 1:10 am:
When r3 is not modified, reload it from regs->orig_r3 to free
volatile registers. This avoids a stack frame for the likely part
of system_call_exception()
This doesn't on m
Le 09/02/2021 à 03:06, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of February 9, 2021 1:10 am:
Combine all tests of regs->msr into a single logical one.
Okay by me unless we choose to do the config option and put these all
under it. I think I would prefer that becaus
From: Segher Boessenkool
> Sent: 09 February 2021 13:51
>
> On Tue, Feb 09, 2021 at 12:36:20PM +1000, Nicholas Piggin wrote:
> > What if you did this?
>
> > +static inline struct task_struct *get_current(void)
> > +{
> > + register struct task_struct *task asm ("r2");
> > +
> > + return task;
Le 09/02/2021 à 03:02, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's message of February 9, 2021 1:10 am:
For book3s/64, FULL_REGS() is 'true' at all time, so the test voids.
For others, non volatile registers are saved inconditionally.
So the verification is pointless.
Should
In commit bf13718bc57a ("powerpc: show registers when unwinding
interrupt frames") we changed our stack dumping logic to show the full
registers whenever we find an interrupt frame on the stack.
However we didn't notice that on 64-bit this doesn't show the final
frame, ie. the interrupt that broug
Le 19/01/2021 à 03:11, Michael Ellerman a écrit :
"Christopher M. Riedl" writes:
On Mon Jan 11, 2021 at 7:22 AM CST, Christophe Leroy wrote:
Le 09/01/2021 à 04:25, Christopher M. Riedl a écrit :
Implement raw_copy_from_user_allowed() which assumes that userspace read
access is open. Use th
Copied from commit 4b842e4e25b1 ("x86: get rid of small
constant size cases in raw_copy_{to,from}_user()")
Very few call sites where that would be triggered remain, and none
of those is anywhere near hot enough to bother.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/uaccess.h |
__put_user_size_allowed() is only called from __put_user_size() now.
Merge them together.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/uaccess.h | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/uaccess.h
b/arch/powerpc/incl
Since commit 17bc43367fc2 ("powerpc/uaccess: Implement
unsafe_copy_to_user() as a simple loop"), raw_copy_to_user_allowed()
is only used by raw_copy_to_user().
Merge raw_copy_to_user_allowed() into raw_copy_to_user().
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/uaccess.h | 8 +-
On Tue, Feb 09, 2021 at 12:36:20PM +1000, Nicholas Piggin wrote:
> What if you did this?
> +static inline struct task_struct *get_current(void)
> +{
> + register struct task_struct *task asm ("r2");
> +
> + return task;
> +}
Local register asm variables are *only* guaranteed to live in th
Em Wed, Feb 03, 2021 at 12:31:48PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Tue, Feb 02, 2021 at 04:02:36PM +0530, Athira Rajeev escreveu:
> >
> >
> > On 18-Jan-2021, at 3:51 PM, kajoljain wrote:
> >
> >
> >
> > On 1/12/21 3:08 PM, Jiri Olsa wrote:
> >
> > On Mon, Dec 2
There are no more users of get_tbl(). Remove it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/vdso/timebase.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/powerpc/include/asm/vdso/timebase.h
b/arch/powerpc/include/asm/vdso/timebase.h
index 881f655caa0a..891c9d5e
get_tbl() is confusing as it returns the content TBL register
on PPC32 but the concatenation of TBL and TBU on PPC64.
Use mftb() instead.
This will allow the removal of get_tbl() in a following patch.
Signed-off-by: Christophe Leroy
---
drivers/spi/spi-mpc52xx.c | 12 ++--
1 file chang
get_tbl() is confusing as it returns the content TBL register
on PPC32 but the concatenation of TBL and TBU on PPC64.
Use mftb() instead.
This will allow the removal of get_tbl() in a following patch.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c | 8 ---
Hi all,
After merging the powerpc tree, today's linux-next build (powerpc
allyesconfig) failed like this:
arch/powerpc/kernel/head_64.o:(__ftr_alt_97+0x0): relocation truncated to fit:
R_PPC64_REL24 (OPD) against symbol `do_page_fault' defined in .opd section in
arch/powerpc/mm/fault.o
arch/pow
In preparation of porting PPC32 to C syscall entry/exit,
create C version of kuap_save_and_lock() and kuap_user_restore() and
kuap_kernel_restore() and kuap_check() and kuap_get_and_check() on 8xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/kup-8xx.h | 33
Move all KUAP management in C.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/kup.h | 50 +---
arch/powerpc/include/asm/interrupt.h | 2 +
arch/powerpc/include/asm/kup.h | 19 +---
arch/powerpc/include/asm/nohash/32/kup-8xx.h
In preparation of porting PPC32 to C syscall entry/exit,
create C version of kuap_save_and_lock() and kuap_user_restore() and
kuap_kernel_restore() and kuap_check() and kuap_get_and_check()
on book3s/32.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/kup.h | 45 ++
In preparation of porting powerpc32 to C syscall entry/exit,
rename kuap_check_amr() and kuap_get_and_check_amr() as kuap_check()
and kuap_get_and_check(), and move in the generic asm/kup.h the stub
for when CONFIG_PPC_KUAP is not selected.
Signed-off-by: Christophe Leroy
---
arch/powerpc/includ
This can be done in C, do it.
Unrolling the loop gains approx. 15% performance.
>From now on, prepare_transfer_to_handler() is only for
interrupts from kernel.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/kup.h | 31 ---
arch/powerpc/include/asm/interr
Only book3s/32 and e500 have significative work to do in
prepare_transfer_to_handler.
Other 32 bit have nothing to do at all.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 6 ++
arch/powerpc/kernel/head_32.h| 2 ++
arch/powerpc/kernel/head_booke.h | 2 ++
3 file
No need to do that is assembly, do it in C.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/interrupt.h | 4 +++-
arch/powerpc/kernel/entry_32.S | 3 +--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/interrupt.h
b/arch/powerpc/include
Save non volatile registers, XER, CTR, MSR and NIP in exception prolog.
Also assign proper value to r2 and r3 there.
For now, recalculate thread pointer in prepare_transfer_to_handler.
It will disappear once KUAP is ported to C.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.
Exception prologs all do the same at the end:
- Save trapno in stack
- Mark stack with exception marker
- Save r0
- Save r3 to r8
Refactor that into a COMMON_EXCEPTION_PROLOG_END macro.
At the same time use r1 instead of r11.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h
transfer_to_handler_cont: is now just a blr.
Directly perform blr in power_save_ppc32_restore().
Also remove useless setting of r11 in e500 version of
power_save_ppc32_restore().
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 2 --
arch/powerpc/kernel/idle_6xx.S | 2 +
The xfer parameter is not used anymore, remove it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h| 2 +-
arch/powerpc/kernel/head_40x.S | 42
arch/powerpc/kernel/head_44x.S | 10 ++--
arch/powerpc/kernel/head_8xx.S | 14 +++---
arch/
In order to get more control in exception prolog, dismantle
all non standard exception macros, finishing with EXC_XFER_STD
and EXC_XFER_LITE and EXC_XFER_TEMPLATE.
Also remove transfer_to_handler_full and ret_from_except and
ret_from_except_full as they are not used anymore.
Last parameter of EXC
Until now, non volatile registers were restored everytime they
were saved, ie using EXC_XFER_STD meant saving and restoring
them while EXC_XFER_LITE meant neither saving not restoring them.
Now that they are always saved, EXC_XFER_STD means to restore
them and EXC_XFER_LITE means to not restore th
In order to increase flexibility, add a macro that will for now
call transfer_to_handler.
As transfer_to_handler doesn't do the actual transfer anymore,
also name it prepare_transfer_to_handler. The following patches
will progressively remove the use of transfer_to_handler label.
Signed-off-by: C
Saving the trap number into the stack goes into
the exception prolog, as EXC_XFER_xxx will soon disappear.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h| 14 -
arch/powerpc/kernel/head_40x.S | 22 +++---
arch/powerpc/kernel/head_8xx.S | 14
Now that non volatile registers are saved at all time, no
need to split bad_page_fault() out of do_page_fault().
Remove handle_page_fault() and use do_page_fault() directly.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 16
arch/powerpc/kernel/head_
All exception handlers take regs as first parameter.
Instead of setting r3 just before each call to a handler, set
it in transfer_to_handler.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 5 ++---
arch/powerpc/kernel/head_32.h| 2 --
arch/powerpc/kernel/he
This patch replaces the PPC32 ASM exceptio exit by C exception exit.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 466 +
1 file changed, 122 insertions(+), 344 deletions(-)
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/
In preparation of handling exception entry and exit in C,
in order to simplify the handling, always save non volatile registers
when entering an exception.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/ptrace.h | 13 -
arch/powerpc/kernel/entry_32.S| 13 +--
Now that the MMU is re-enabled before calling the transfer function,
we don't need anymore that hack with the address of the handler and
the return function sitting just after the 'bl' to the transfer
fonction, that that function is retrieving via a read
relative to 'lr'.
Do a regular call to the
Refactor booke critical registers saving into a few macros
and move it into the exception prolog directly.
Keep the dedicated transfert_to_handler entry point for the
moment allthough they are empty. They will be removed in a
later patch to reduce churn.
Signed-off-by: Christophe Leroy
---
arch
Now that the prolog continuation is separated in .text, give it a name
and mark it _ASM_NOKPROBE_SYMBOL.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h| 12 +++-
arch/powerpc/kernel/head_40x.S | 22 --
arch/powerpc/kernel/head_8xx.S
The space in the head section is rather constrained by the fact that
exception vectors are spread every 0x100 bytes and sometimes we
need to have "out of line" code because it doesn't fit.
Now that we are enabling MMU early in the prolog, take that opportunity
to jump somewhere else in the .text s
Everywhere where it is possible, use START_EXCEPTION().
This will help for proper exception init in future patches.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_40x.S | 12 +--
arch/powerpc/kernel/head_8xx.S | 27 +
arch/powerpc/kernel
For consistancy, add in the macro the label used by exception prolog
to branch to stack overflow processing.
While at it, enclose the macro in #ifdef CONFIG_VMAP_STACK on the 8xx
as already done on book3s/32.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h| 3 ++-
arch
The check of the emergency context initialisation in
vmap_stack_overflow is buggy for the SMP case, as it
compares r1 with 0 while in the SMP case r1 is offseted
by the CPU id.
Instead of fixing it, just perform static initialisation
of the first emergency context.
Signed-off-by: Christophe Leroy
On 40x and 8xx, kernel text is pinned.
On book3s/32, kernel text is mapped by BATs.
Enable instruction translation at the same time as data translation, it
makes things simpler.
In syscall handler, MSR_RI can also be set at the same time because
srr0/srr1 are already saved and r1 is set properly.
8xx requires to tag the DAR with a magic value in order to
detect fixup DAR on faults generated by 'dcbX', as the 8xx
forgets to update the DAR for those faults.
Do the tagging as early as possible, that is before enabling MMU.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h
If the code can use a stack in vm area, it can also use a
stack in linear space.
Simplify code by removing old non VMAP stack code on PPC32.
That means the data translation is now re-enabled early in
exception prolog in all cases, not only when using VMAP stacks.
While we are touching EXCEPTION_
ksp_limit is there to help detect stack overflows.
That is specific to ppc32 as it was removed from ppc64 in
commit cbc9565ee826 ("powerpc: Remove ksp_limit on ppc64").
There are other means for detecting stack overflows.
As ppc64 has proven to not need it, ppc32 should be able to do
without it t
8xx has registers SPRN_NRI, SPRN_EID and SPRN_EIE for changing
MSR EE and RI.
Use SPRN_EID in exception prolog to set RI.
On an 8xx, it reduces the null_syscall test by 3 cycles.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h | 2 ++
1 file changed, 2 insertions(+)
diff --g
The handling of SPRN_DBCR0 and other registers can easily
be done in C instead of ASM.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/interrupt.h | 7 +++
arch/powerpc/kernel/entry_32.S | 23 ---
2 files changed, 7 insertions(+), 23 deletions(-)
diff
There is no need for this to be in asm,
use the new interrupt entry wrapper.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/interrupt.h | 3 +++
arch/powerpc/include/asm/ppc_asm.h | 10 --
arch/powerpc/kernel/entry_32.S | 1 -
3 files changed, 3 insertions(+), 11
In order the enable MMU early in exception prolog, implement
CONFIG_VMAP_STACK principles in critical exception prolog.
There is no intention to use CONFIG_VMAP_STACK on 40x,
but related code will be used to enable MMU early in exception
in a later patch.
Also address (critirq_ctx-PAGE_OFFSET) di
In order to ease preparation for CONFIG_VMAP_STACK, reorder
a few instruction, especially save r1 into stack frame earlier.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_40x.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_40x.
Ensure normal exception handler are able to manage stuff with
MMU enabled. For that we use CONFIG_VMAP_STACK related code
allthough there is no intention to really activate CONFIG_VMAP_STACK
on powerpc 40x for the moment.
40x uses SPRN_DEAR instead of SPRN_DAR and SPRN_ESR instead of
SPRN_DSISR. T
There is no need for this to be in asm anymore,
use the new interrupt entry wrapper.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/interrupt.h | 4 ++
arch/powerpc/kernel/entry_32.S | 58
2 files changed, 4 insertions(+), 58 deletions(-)
diff -
SPRN_SPRG_SCRATCH5 is used to save SPRN_PID.
SPRN_SPRG_SCRATCH6 is already available.
SPRN_PID is only 8 bits. We have r12 that contains CR.
We only need to preserve CR0, so we have space available in r12
to save PID.
Keep PID in r12 and free up SPRN_SPRG_SCRATCH5.
Then In TLB miss handlers, ins
Change CRITICAL_EXCEPTION_PROLOG macro to a gas macro to
remove the ugly ; and \ on each line.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_40x.S | 71 +-
1 file changed, 36 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/kernel/head_40x.
This series aims at porting interrupt entry/exit in C on PPC32, using
the work already merged for PPC64.
First part do minimal changes in 40x in order to be able to enable MMU
earlier in exception entry.
Second part prepares and switches interrupt exit in C.
Third part moves more and more things
In order to be able to switch MMU on in exception prolog, save
SRR0 and SRR1 earlier.
Also save r10 and r11 into stack earlier to better match with the
normal exception prolog.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 9 -
arch/powerpc/kernel/head_40x.S | 8 +
THREAD_ALIGN_SHIFT = THREAD_SHIFT + 1 = PAGE_SHIFT + 1
Maximum PAGE_SHIFT is 18 for 256k pages so
THREAD_ALIGN_SHIFT is 19 at the maximum.
No need to clobber cr1, it can be preserved when moving r1
into CR when we check stack overflow.
This reduces the number of instructions in Machine Check Exce
Thresholding, a performance monitoring unit feature, can be
used to identify marked instructions which take more than
expected cycles between start event and end event.
Threshold compare (thresh_cmp) bits are programmed in MMCRA
register. In Power9, thresh_cmp bits were part of the
event code. But
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