[PATCH] powerpc/mm: don't log user reads to 0xffffffff

2019-12-22 Thread Christophe Leroy
Running vdsotest leaves many times the following log: [ 79.629901] vdsotest[396]: User access of kernel address () - exploit attempt? (uid: 0) A pointer set to (-1) is likely a programming error similar to a NULL pointer and is not worth logging as an exploit attempt. Don't log user a

[PATCH kernel v3] powerpc/book3s64: Fix error handling in mm_iommu_do_alloc()

2019-12-22 Thread Alexey Kardashevskiy
The last jump to free_exit in mm_iommu_do_alloc() happens after page pointers in struct mm_iommu_table_group_mem_t were already converted to physical addresses. Thus calling put_page() on these physical addresses will likely crash. This moves the loop which calculates the pageshift and converts pa

[PATCH kernel] vfio/spapr/nvlink2: Skip unpinning pages on error exit

2019-12-22 Thread Alexey Kardashevskiy
The nvlink2 subdriver for IBM Witherspoon machines preregisters GPU memory in the IOMMI API so KVM TCE code can map this memory for DMA as well. This is done by mm_iommu_newdev() called from vfio_pci_nvgpu_regops::mmap. In an unlikely event of failure the data->mem remains NULL and since mm_iommu_

Re: [PATCH] powerpc/book3s64: Fix error handling in mm_iommu_do_alloc()

2019-12-22 Thread Alexey Kardashevskiy
On 20/12/2019 20:57, Jan Kara wrote: > On Fri 20-12-19 16:06:05, Alexey Kardashevskiy wrote: >> >> >> On 11/12/2019 21:42, Jan Kara wrote: >>> The last jump to free_exit in mm_iommu_do_alloc() happens after page >>> pointers in struct mm_iommu_table_group_mem_t were already converted to >>> phys

Re: [PATCH v11 00/25] mm/gup: track dma-pinned pages: FOLL_PIN

2019-12-22 Thread Leon Romanovsky
On Fri, Dec 20, 2019 at 03:54:55PM -0800, John Hubbard wrote: > On 12/20/19 10:29 AM, Leon Romanovsky wrote: > ... > >> $ ./build.sh > >> $ build/bin/run_tests.py > >> > >> If you get things that far I think Leon can get a reproduction for you > > > > I'm not so optimistic about that. > > > > OK, I

[PATCH V4 14/14] powerpc/vas: Free send window in VAS instance after credits returned

2019-12-22 Thread Haren Myneni
NX may be processing requests while trying to close window. Wait until all credits are returned and then free send window from VAS instance. Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-window.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/

[PATCH V4 13/14] powerpc/vas: Display process stuck message

2019-12-22 Thread Haren Myneni
Process can not close send window until all requests are processed. Means wait until window state is not busy and send credits are returned. Display debug message in case taking longer to close the window. Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-window.c | 27 +++

[PATCH V4 12/14] powerpc/VAS: Return credits after handling fault

2019-12-22 Thread Haren Myneni
NX expects OS to return credit for send window after processing each fault. Also credit has to be returned even for fault window. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-fault.c | 10 ++ arch/powerpc/platforms/powernv/vas-

[PATCH V4 11/14] powerpc/vas: Do not use default credits for receive window

2019-12-22 Thread Haren Myneni
System checkstops if RxFIFO overruns with more requests than the maximum possible number of CRBs allowed in FIFO at any time. So max credits value (rxattr.wcreds_max) is set and is passed to vas_rx_win_open() by the the driver. Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas

[PATCH V4 10/14] powerpc/vas: Print CRB and FIFO values

2019-12-22 Thread Haren Myneni
Dump FIFO entry values if could not find send window and print CRB for debugging. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-fault.c | 41 ++ 1 file changed, 41 insertions(+) diff --git a/arch/powerpc/plat

[PATCH V4 09/14] powerpc/vas: Update CSB and notify process for fault CRBs

2019-12-22 Thread Haren Myneni
For each fault CRB, update fault address in CRB (fault_storage_addr) and translation error status in CSB so that user space can touch the fault address and resend the request. If the user space passed invalid CSB address send signal to process with SIGSEGV. Signed-off-by: Sukadev Bhattiprolu Si

[PATCH V4 06/14] powerpc/vas: Setup thread IRQ handler per VAS instance

2019-12-22 Thread Haren Myneni
Setup thread IRQ handler per each VAS instance. When NX sees a fault on CRB, kernel gets an interrupt and vas_fault_handler will be executed to process fault CRBs. Read all valid CRBs from fault FIFO, determine the corresponding send window from CRB and process fault requests. Signed-off-by: Suk

[PATCH V4 08/14] powerpc/vas: Take reference to PID and mm for userspace windows

2019-12-22 Thread Haren Myneni
Process close windows after its requests are completed. In multi-thread applications, child can open a window but release FD will not be called upon its exit. Parent thread will be closing it later upon its exit. The parent can also send NX requests with this window and NX can generate page faul

[PATCH V4 07/14] powerpc/vas: Register NX with fault window ID and IRQ port value

2019-12-22 Thread Haren Myneni
For each user space send window, register NX with fault window ID and port value so that NX paste CRBs in this fault FIFO when it sees fault on the request buffer. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas-window.c | 15 +

[PATCH V4 05/14] powerpc/vas: Setup fault window per VAS instance

2019-12-22 Thread Haren Myneni
Setup fault window for each VAS instance. When NX gets fault on request buffer, write fault CRBs in the corresponding fault FIFO and then sends an interrupt to the OS. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/Makefile | 2 +- arch

[PATCH V4 04/14] powerpc/vas: Alloc and setup IRQ and trigger port address

2019-12-22 Thread Haren Myneni
Alloc IRQ and get trigger port address for each VAS instance. Kernel register this IRQ per VAS instance and sets this port for each send window. NX interrupts the kernel when it sees page fault. Signed-off-by: Haren Myneni --- arch/powerpc/platforms/powernv/vas.c | 34 +

[PATCH V4 03/14] powerpc/vas: Define nx_fault_stamp in coprocessor_request_block

2019-12-22 Thread Haren Myneni
Kernel sets fault address and status in CRB for NX page fault on user space address after processing page fault. User space gets the signal and handles the fault mentioned in CRB by bringing the page in to memory and send NX request again. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Haren

[PATCH V4 02/14] powerpc/xive: Define xive_native_alloc_get_irq_info()

2019-12-22 Thread Haren Myneni
pnv_ocxl_alloc_xive_irq() in ocxl.c allocates IRQ and gets trigger port address. VAS also needs this function, but based on chip ID. So moved this common function to xive/native.c. Signed-off-by: Haren Myneni --- arch/powerpc/include/asm/xive.h | 2 ++ arch/powerpc/platforms/powernv/ocx

[PATCH V4 01/14] powerpc/xive: Define xive_native_alloc_irq_on_chip()

2019-12-22 Thread Haren Myneni
This function allocates IRQ on a specific chip. VAS needs per chip IRQ allocation and will have IRQ handler per VAS instance. Signed-off-by: Haren Myneni --- arch/powerpc/include/asm/xive.h | 9 - arch/powerpc/sysdev/xive/native.c | 6 +++--- 2 files changed, 11 insertions(+), 4 dele

[PATCH V4 00/14] powerpc/vas: Page fault handling for user space NX requests

2019-12-22 Thread Haren Myneni
On power9, Virtual Accelerator Switchboard (VAS) allows user space or kernel to communicate with Nest Accelerator (NX) directly using COPY/PASTE instructions. NX provides verious functionalities such as compression, encryption and etc. But only compression (842 and GZIP formats) is supported in L

Re: [PATCH] powerpc/mpc85xx: also write addr_h to spin table for 64bit boot entry

2019-12-22 Thread Michael Ellerman
yingjie_...@126.com writes: > From: Bai Yingjie > > CPU like P4080 has 36bit physical address, its DDR physical > start address can be configured above 4G by LAW registers. > > For such systems in which their physical memory start address was > configured higher than 4G, we need also to write addr