Remove duplicate headers which are included twice.
Signed-off-by: Sabyasachi Gupta
Signed-off-by: Souptick Joarder
---
tools/testing/selftests/gpio/gpio-mockup-chardev.c | 1 -
tools/testing/selftests/net/udpgso.c| 1 -
tools/testing/selftests/powerpc/pmu/ebb/fo
Sasha Levin writes:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a "Fixes:" tag,
> fixing commit: cf43d3b26452 powerpc: Enable pkey subsystem.
>
> The bot has tested the following trees: v4.20.11, v4.19.24.
>
> v4.19.24: Failed to apply! Possible de
When the hash MMU is active the AMR, IAMR and UAMOR are used for
pkeys. The AMR is directly writable by user space, and the UAMOR masks
those writes, meaning both registers are effectively user register
state. The IAMR is used to create an execute only key.
Also we must maintain the value of at le
When testing DLPAR CPU add/remove on a system under stress,
pseries_cpu_die() doesn't wait long enough for a CPU to die:
[ 446.983944] cpu 148 (hwid 148) Ready to die...
[ 446.984062] cpu 149 (hwid 149) Ready to die...
[ 446.993518] cpu 150 (hwid 150) Ready to die...
[ 446.993543] Querying DEA
On 22/02/19 16:06, lantianyu1...@gmail.com wrote:
> From: Lan Tianyu
>
> This patchset is to introduce hv ept tlb range list flush function
> support in the KVM MMU component. Flushing ept tlbs of several address
> range can be done via single hypercall and new list flush function is
> used in th
We added runtime allocation of 16G pages in
commit 4ae279c2c96a ("powerpc/mm/hugetlb: Allow runtime allocation of 16G.")
That was done to enable 16G allocation on PowerNV and KVM config. In case of KVM
config, we mostly would have the entire guest RAM backed by 16G hugetlb pages
for
this to work.
int hyperv_fill_flush_guest_mapping_list(
struct hv_guest_mapping_flush_list *flush,
- u64 start_gfn, u64 pages)
+ int offset, u64 start_gfn, u64 pages)
{
u64 cur = start_gfn;
u64 additional_pages;
- int gpa_n = 0;
+ int gpa_n
Hi,
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag,
fixing commit: cf43d3b26452 powerpc: Enable pkey subsystem.
The bot has tested the following trees: v4.20.11, v4.19.24.
v4.19.24: Failed to apply! Possible dependencies:
41f4e631daf8 ("KVM: P
Michael Ellerman writes:
> "Aneesh Kumar K.V" writes:
>
>> After we ALIGN up the address we need to make sure we didn't overflow
>> and resulted in zero address. In that case, we need to make sure that
>> the returned address is greater than mmap_min_addr.
>>
>> Also when doing top-down search t
On Fri, Feb 15, 2019 at 11:23 PM Paolo Bonzini wrote:
>
> On 15/02/19 16:05, Tianyu Lan wrote:
> > Yes, you are right. Thanks to point out and will fix. The last_level
> > flag is to avoid adding middle page node(e.g, PGD, PMD)
> > into flush list. The address range will be duplicated if adding bo
From: Lan Tianyu
This patch is to add flush parameter for kvm_aga_hva() and move tlb
flush from kvm_mmu_notifier_clear_flush_young() to kvm_age_hva().
kvm_age_hva() can check whether tlb flush is necessary when
return value young is more than 0. Flush tlb if both conditions
are met.
Signed-off-b
From: Lan Tianyu
This patch is to use tlb range flush to flush memslot's in the
kvm_vm_ioctl_get/clear_dirty_log() instead of flushing tlbs
of entire ept page table when range flush is available.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/mmu.c | 8 +---
arch/x86/kvm/mmu.h | 7 +++
a
From: Lan Tianyu
This patch is to add kvm_get_memslot() to get struct kvm_memory_slot
via slot it and remove redundant codes. The function will also be used
in the following changes.
Signed-off-by: Lan Tianyu
---
include/linux/kvm_host.h | 1 +
virt/kvm/kvm_main.c | 45 ++
From: Lan Tianyu
This patch is to flush tlb directly in the kvm_mmu_slot_gfn_write_protect()
when range flush is available.
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/mmu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 7a862c56b954..60b1
From: Lan Tianyu
This patch is to use range flush to flush tlbs of input struct
kvm_mmu_page in the sync_page(). If range flush is not available,
kvm_flush_remote_tlbs_with_address() will call kvm_flush_remote_tlbs().
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/paging_tmpl.h | 5 +++--
1 file c
From: Lan Tianyu
This patch is to introduce tlb flush with range list interface and use
struct kvm_mmu_page as list entry. Use flush list function in the
kvm_mmu_commit_zap_page().
Signed-off-by: Lan Tianyu
---
arch/x86/kvm/mmu.c | 24 +++-
1 file changed, 23 insertions(+),
From: Lan Tianyu
Populate ranges on the flush list into struct hv_guest_mapping_flush_list
when flush list is available in the struct kvm_tlb_range.
Signed-off-by: Lan Tianyu
---
Change since v2:
- Fix calculation of flush pages in the kvm_fill_hv_flush_list_func()
---
arch/x86/include
From: Lan Tianyu
Add parameter offset to specify start position to add flush ranges in
guest address list of struct hv_guest_mapping_flush_list.
Signed-off-by: Lan Tianyu
---
arch/x86/hyperv/nested.c| 4 ++--
arch/x86/include/asm/mshyperv.h | 2 +-
arch/x86/kvm/vmx/vmx.c | 2 +
From: Lan Tianyu
This patchset is to introduce hv ept tlb range list flush function
support in the KVM MMU component. Flushing ept tlbs of several address
range can be done via single hypercall and new list flush function is
used in the kvm_mmu_commit_zap_page() and FNAME(sync_page). This patchse
Hi Jonathan,
Thanks for your comments, I'll make a new version of the patch based
on your input.
William, I'll rebase the next version on top of your branch.
I'm glad the counter subsystem effort is progressing :)
Patrick Havelange.
On Thu, Feb 21, 2019 at 9:27 AM William Breathitt Gray
wrot
On Fri, Feb 22, 2019 at 02:43:41PM +1100, Michael Ellerman wrote:
> Stephen Rothwell writes:
>
> > Hi all,
> >
> > Today's linux-next merge of the powerpc tree got a conflict in:
> >
> > arch/powerpc/kernel/dma-swiotlb.c
> >
> > between commit:
> >
> > cfced786969c ("dma-mapping: remove the d
This control is to be used by the H_INT_RESET hcall from QEMU. Its
purpose is to clear all configuration of the sources and EQs. This is
necessary in case of a kexec (for a kdump kernel for instance) to make
sure that no remaining configuration is left from the previous boot
setup so that the new k
The KVM XICS-over-XIVE device and the proposed KVM XIVE native device
implement an IRQ space for the guest using the generic IPI interrupts
of the XIVE IC controller. These interrupts are allocated at the OPAL
level and "mapped" into the guest IRQ number space in the range 0-0x1FFF.
Interrupt manag
Each source is associated with an Event State Buffer (ESB) with a
even/odd pair of pages which provides commands to manage the source:
to trigger, to EOI, to turn off the source for instance.
The custom VM fault handler will deduce the guest IRQ number from the
offset of the fault, and the ESB pag
When the VM boots, the CAS negotiation process determines which
interrupt mode to use and invokes a machine reset. At that time, the
previous KVM interrupt device is 'destroyed' before the chosen one is
created. Upon destruction, the vCPU interrupt presenters using the KVM
device should be cleared
When migration of a VM is initiated, a first copy of the RAM is
transferred to the destination before the VM is stopped, but there is
no guarantee that the EQ pages in which the event notification are
queued have not been modified.
To make sure migration will capture a consistent memory state, the
The 'destroy' method is currently used to destroy all devices when the
VM is destroyed after the vCPUs have been freed.
This new KVM ioctl exposes the same KVM device method. It acts as a
software reset of the VM to 'destroy' selected devices when necessary
and perform the required cleanups on the
Some KVM devices will want to handle special mappings related to the
underlying HW. For instance, the XIVE interrupt controller of the
POWER9 processor has MMIO pages for thread interrupt management and
for interrupt source control that need to be exposed to the guest when
the OS has the required s
This control will be used by the H_INT_SYNC hcall from QEMU.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/uapi/asm/kvm.h| 1 +
arch/powerpc/kvm/book3s_xive_native.c | 34 ++
Documentation/virtual/kvm/devices/xive.txt | 9 ++
3 files changed, 44
Each thread has an associated Thread Interrupt Management context
composed of a set of registers. These registers let the thread handle
priority management and interrupt acknowledgment. The most important
are :
- Interrupt Pending Buffer (IPB)
- Current Processor Priority (CPPR)
At a VCPU level, the state of the thread interrupt management
registers needs to be collected. These registers are cached under the
'xive_saved_state.w01' field of the VCPU when the VPCU context is
pulled from the HW thread. An OPAL call retrieves the backup of the
IPB register in the underlying XI
These controls will be used by the H_INT_SET_QUEUE_CONFIG and
H_INT_GET_QUEUE_CONFIG hcalls from QEMU. They will also be used to
restore the configuration of the XIVE EQs in the KVM device and to
capture the internal runtime state of the EQs. Both 'get' and 'set'
rely on an OPAL call to access from
The user interface exposes a new capability to let QEMU connect the
vCPU to the XIVE KVM device if required. The capability is only
advertised on a PowerNV Hypervisor as support for nested guests
(pseries KVM Hypervisor) is not yet available.
Internally, the interface to the new KVM device is prot
Hello,
On the POWER9 processor, the XIVE interrupt controller can control
interrupt sources using MMIOs to trigger events, to EOI or to turn off
the sources. Priority management and interrupt acknowledgment is also
controlled by MMIO in the CPU presenter subengine.
PowerNV/baremetal Linux runs na
The associated HW interrupt source is simply allocated at the OPAL/HW
level and then MASKED. KVM only needs to know about its type: LSI or
MSI.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/uapi/asm/kvm.h| 5 +
arch/powerpc/kvm/book3s_xive.h | 10 ++
arch/powerp
This control will be used by the H_INT_SET_SOURCE_CONFIG hcall from
QEMU and also to restore the configuration of the source in the KVM
device.
The XIVE internal IRQ structure is extended with the value of the
Effective Interrupt Source Number. The EISN is the interrupt number
pushed in the event
This is the basic framework for the new KVM device supporting the XIVE
native exploitation mode. The user interface exposes a new KVM device
to be created by QEMU when running on a L0 hypervisor only. Support
for nested guests is not available yet.
Signed-off-by: Cédric Le Goater
---
arch/powerp
The support for XIVE native exploitation mode in Linux/KVM needs a
couple more OPAL calls to configure the sPAPR guest and to get/set the
state of the XIVE internal structures.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/opal-api.h | 11 ++-
arch/powerpc/include/asm/op
Christophe Leroy writes:
> Le 22/02/2019 à 08:14, Stephen Rothwell a écrit :
>> Hi all,
>>
>> After merging the powerpc tree, today's linux-next build (powerpc
>> allyesconfig) failed like this:
>>
>> make[4]: *** No rule to make target 'arch/powerpc/mm/ptdump/core.o', needed
>> by 'arch/powerp
Hello Dan,
Le 22/02/2019 à 11:43, Dan Carpenter a écrit :
Hello Christophe Leroy,
The patch 7c91efce1608: "powerpc/mm: dump block address translation
on book3s/32" from Dec 3, 2018, leads to the following static checker
warning:
arch/powerpc/mm/dump_bats.c:20 pp_601()
warn: b
Hello Christophe Leroy,
The patch 7c91efce1608: "powerpc/mm: dump block address translation
on book3s/32" from Dec 3, 2018, leads to the following static checker
warning:
arch/powerpc/mm/dump_bats.c:20 pp_601()
warn: both sides of ternary the same: '"RWX"'
arch/powerpc/mm/dump_ba
On Mon, 2019-02-18 at 05:58:01 UTC, Alexey Kardashevskiy wrote:
> The compound IOMMU group rework moved iommu_register_group() together in
> pnv_pci_ioda_setup_iommu_api() (which is a part of ppc_md.pcibios_fixup).
> As the result, pnv_ioda_setup_bus_iommu_group() does not create groups
> any more,
On Sat, 2017-09-02 at 06:47:26 UTC, "Robert P. J. Day" wrote:
> While the current kernel drivers/of/ code allows developers to be
> sloppy and use a DTS status value of "ok", the current DTSpec 0.1
> makes it clear that the proper spelling is "okay", so fix the small
> number of PowerPC .dts files
On Thu, 2019-02-21 at 10:37:53 UTC, Christophe Leroy wrote:
> There is no reason to re-read each time the pointer at
> location 0xf0 as it is fixed and known.
>
> Signed-off-by: Christophe Leroy
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/40058337f23f79212f92ed5ef06
On Thu, 2019-02-21 at 02:38:49 UTC, Paul Mackerras wrote:
> This makes the handling of machine check interrupts that occur inside
> a guest simpler and more robust, with less done in assembler code and
> in real mode.
>
> Now, when a machine check occurs inside a guest, we always get the
> machine
On Wed, 2019-02-20 at 08:55:00 UTC, Michael Ellerman wrote:
> kvmhv_p9_guest_entry() implements a fast-path guest entry for Power9
> when guest and host are both running with the Radix MMU.
>
> Currently in that path we don't save the host AMR (Authority Mask
> Register) value, and we always resto
On Mon, 2019-02-18 at 12:28:36 UTC, Christophe Leroy wrote:
> This patch moves the files related to page table dump in a
> dedicated subdirectory.
>
> The purpose is to clean a bit arch/powerpc/mm by regrouping
> multiple files handling a dedicated function.
>
> Signed-off-by: Christophe Leroy
On Mon, 2019-02-18 at 12:25:20 UTC, Christophe Leroy wrote:
> When using KASAN, there are parts of the shadow area where all
> pages are mapped to the kasan_early_shadow_page. It is pointless
> to dump one line for each of those pages (in the example below there
> are 7168 entries pointing to the s
On Fri, 2019-02-15 at 10:32:02 UTC, Christophe Leroy wrote:
> Commit d4fde568a34a ("powerpc/64: Use optimized checksum routines on
> little-endian") converted last powerpc user of GENERIC_CSUM.
>
> This patch does a final cleanup dropping the Kconfig GENERIC_CSUM
> option which is always 'n', and
On Fri, 2019-02-15 at 06:14:00 UTC, Michael Ellerman wrote:
> GCC 8 warns about the logic in vr_get/set(), which with -Werror breaks
> the build:
>
> In function âÂÂuser_regset_copyinâÂÂ,
> inlined from âÂÂvr_setâ at arch/powerpc/kernel/ptrace.c:628:9:
> include/linux/regse
On Fri, 2019-02-15 at 10:20:20 UTC, Nicholas Piggin wrote:
> The slbfee. instruction must have bit 24 of RB clear, failure to do
> so can result in false negatives that result in incorrect assertions.
>
> This is not obvious from the ISA v3.0B document, which only says:
>
> The hardware ignor
On Fri, 2019-02-15 at 00:48:11 UTC, Oliver O'Halloran wrote:
> There's no need to the custom getter/setter functions so we should remove
> them in favour of using the generic one. While we're here, change the type
> of eeh_max_freeze to u32 and print the value in decimal rather than
> hex because p
On Thu, 2019-02-14 at 06:45:40 UTC, "Aneesh Kumar K.V" wrote:
> When updating page tables, we need to make sure we fill the page table
> entry valid bit. We should be using page table populate interface for
> updating the table entries. The page table 'set' interface allows
> updating the raw value
On Wed, 2019-02-13 at 11:15:09 UTC, "Aneesh Kumar K.V" wrote:
> From: Michael Ellerman
>
> This patch updates the kernel none linear virtual map area size to 512TB
> with 64K page size and hash translation mode. We allocate one context
> for the vmalloc region and hence the max virtual area size
On Tue, 2019-02-12 at 00:58:29 UTC, Paul Mackerras wrote:
> Commit 24be85a23d1f ("powerpc/powernv: Clear PECE1 in LPCR via stop-api
> only on Hotplug", 2017-07-21) added two calls to opal_slw_set_reg()
> inside pnv_cpu_offline(), with the aim of changing the LPCR value in
> the SLW image to disable
On Wed, 2019-02-13 at 07:01:02 UTC, Christoph Hellwig wrote:
> The pasemi driver never set a DMA mask, and given that the powerpc
> DMA mapping routines never check it this worked ok so far. But the
> generic dma-direct code which I plan to switch on for powerpc checks
> the DMA mask and fails uns
On Mon, 2019-02-11 at 00:20:01 UTC, Andrew Donnellan wrote:
> From: Michael Ellerman
>
> In cpufeatures_process_feature(), if a provided CPU feature is unknown and
> enable_unknown is false, we erroneously print that the feature is being
> enabled and return true, even though no feature has been
On Fri, 2019-02-08 at 15:02:55 UTC, Christophe Leroy wrote:
> map_hugetlb maps 256Mbytes of memory with default hugepage size.
>
> This patch allows the user to pass the size and page shift as an
> argument in order to use different size and page size.
>
> Signed-off-by: Christophe Leroy
Applie
On Fri, 2019-02-08 at 14:33:19 UTC, Mark Cave-Ayland wrote:
> Commit 8792468da5e1 "powerpc: Add the ability to save FPU without giving it
> up"
> unexpectedly removed the MSR_FE0 and MSR_FE1 bits from the bitmask used to
> update the MSR of the previous thread in __giveup_fpu() causing a KVM-PR Ma
On Fri, 2019-02-08 at 12:34:16 UTC, Michael Ellerman wrote:
> In commit 7820856a4fcd ("powerpc/mm/book3e/64: Remove unsupported
> 64Kpage size from 64bit booke") we dropped the 64K page size support
> from the 64-bit nohash (Book3E) code.
>
> But we didn't update the dependencies of the PPC_64K_PA
On Thu, 2019-02-07 at 02:49:35 UTC, Michael Ellerman wrote:
> The recent rework of PCI kconfig symbols exposed an existing bug in
> the CURRITUCK kconfig logic.
>
> It selects PPC4xx_PCI_EXPRESS which depends on PCI, but PCI is user
> selectable and might be disabled, leading to a warning:
>
>
On Thu, 2019-01-31 at 10:30:22 UTC, Peter Xu wrote:
> The change_pte() notifier was designed to use as a quick path to
> update secondary MMU PTEs on write permission changes or PFN changes.
> For KVM, it could reduce the vm-exits when vcpu faults on the pages
> that was touched up by KSM. It's no
On Thu, 2019-01-31 at 10:10:31 UTC, Christophe Leroy wrote:
> 40x/booke have another path to reach 3f from transfer_to_handler,
> make sure it also calls ACCOUNT_CPU_USER_ENTRY() when
> CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is selected.
>
> Signed-off-by: Christophe Leroy
Applied to powerpc next, th
On Fri, 2019-01-25 at 12:34:20 UTC, Christophe Leroy wrote:
> For pages without _PAGE_USER, PP field is 00
> For pages with _PAGE_USER, PP field is 10 for RW and 11 for RO.
>
> This patch sets _PAGE_USER to 0x002 and _PAGE_RW to 0x001
> is order to simplify TLB handling by reducing amount of shift
On Fri, 2019-01-25 at 12:03:55 UTC, Christophe Leroy wrote:
> The 83xx has 8 SPRG registers and uses at least SPRG4
> for DTLB handling LRU.
>
> Fixes: 2319f1239592 ("powerpc/mm: e300c2/c3/c4 TLB errata workaround")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Christophe Leroy
Applied to powerp
On Tue, 2019-01-22 at 14:11:24 UTC, Christophe Leroy wrote:
> Looks like book3s/32 doesn't set RI on machine check, so
> checking RI before calling die() will always be fatal
> allthought this is not an issue in most cases.
>
> Fixes: b96672dd840f ("powerpc: Machine check interrupt is a non-maskab
On Tue, 2019-01-22 at 13:54:57 UTC, Christophe Leroy wrote:
> All callers of mftb() expect 'unsigned long', and the function itself
> only returns lower part of the TB so it really is 'unsigned long'
> not 'unsigned long long'
>
> Signed-off-by: Christophe Leroy
Applied to powerpc next, thanks.
On Tue, 2019-01-22 at 13:52:04 UTC, Christophe Leroy wrote:
> MSR[RI] has already been cleared a few lines above.
>
> Signed-off-by: Christophe Leroy
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/ab44840df1dcd1a10c514aa2938c47f5
cheers
On Tue, 2019-01-15 at 06:37:36 UTC, Michael Ellerman wrote:
> We weren't using SYSCALL_DEFINE for sys_switch_endian(), which means
> it wasn't able to be traced by CONFIG_FTRACE_SYSCALLS.
>
> By using the macro we create the right metadata and the syscall is
> visible. eg:
>
> # cd /sys/kernel/
On Tue, 2018-12-18 at 06:53:41 UTC, Christophe Leroy wrote:
> When no machine description matches, display it clearly
> before looping forever.
>
> Signed-off-by: Christophe Leroy
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/e995265252fad3cf10cec6821ff0870c
cheers
On Thu, 2018-12-13 at 08:08:11 UTC, Christophe Leroy wrote:
> When disassembling InstructionTLBError we get the following messy code:
>
> c000138c: 7d 84 63 78 mr r4,r12
> c0001390: 75 25 58 00 andis. r5,r9,22528
> c0001394: 75 2a 40 00 andis. r10,r9,16384
> c0
On Sat, 2018-12-08 at 23:48:27 UTC, Tyrel Datwyler wrote:
> The Processor Utilzation of Resource Registers (PURR) provide an estimate of
> resources used by a cpu thread. Section 7.6 in Book III of the ISA outlines
> how to calculate the percentage of shared resources for threads using the
> ratio
On Mon, 2018-11-26 at 02:01:05 UTC, Nicholas Piggin wrote:
> The NMI IPI timeout logic is broken, if __smp_send_nmi_ipi times out
> on the first condition, delay_us will be zero which will send it into
> the second spin loop with no timeout so it will spin forever.
>
> Fixes: 5b73151fff63 ("powerp
On Thu, Feb 21, 2019 at 02:28:48PM +1100, Jordan Niethe wrote:
> Currently trying to build without IOMMU support will fail:
>
> (.text+0x1380): undefined reference to `kvmppc_h_get_tce'
> (.text+0x1384): undefined reference to `kvmppc_rm_h_put_tce'
> (.text+0x149c): undefined reference to `k
On Thu, Feb 21, 2019 at 02:44:14PM +1100, Alexey Kardashevskiy wrote:
> The anon fd's ops releases the KVM reference in the release hook.
> However we reference the KVM object after we create the fd so there is
> small window when the release function can be called and
> dereferenced the KVM object
On Tue, Feb 12, 2019 at 03:37:45PM +1100, Alexey Kardashevskiy wrote:
> The SPAPR TCE KVM device references all hardware IOMMU tables assigned to
> some IOMMU group to ensure that in-kernel KVM acceleration of H_PUT_TCE
> can work. The tables are references when an IOMMU group gets registered
> wit
On Thu, Feb 07, 2019 at 03:56:50PM +1100, Suraj Jitindar Singh wrote:
> Devices on the KVM_FAST_MMIO_BUS by definition have length zero and are
> thus used for notification purposes rather than data transfer. For
> example eventfd for virtio devices.
>
> This means that when emulating mmio instruc
On Tue, Feb 19, 2019 at 02:53:45PM +1100, Suraj Jitindar Singh wrote:
> This adds an entry to the kvm_stats_debugfs directory which provides the
> number of large (2M or 1G) pages which have been used to setup the guest
> mappings.
>
> Signed-off-by: Suraj Jitindar Singh
Thanks, applied to my kv
> -Original Message-
> From: Horia Geantă
> Sent: Thursday, February 21, 2019 6:38 PM
> To: Leo Li
> Cc: Y.b. Lu ; linuxppc-dev@lists.ozlabs.org;
> linux-arm-ker...@lists.infradead.org; linux-ker...@vger.kernel.org
> Subject: [PATCH] soc: fsl: guts: make fsl_guts_get_svr() static
>
> T
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