On (02/08/19 13:55), Steven Rostedt wrote:
[..]
> > + if (len) {
> > + /*
> > +* Order the stores above in vsnprintf() vs the store of the
> > +* space below which joins the two strings. Note this doesn't
> > +* make the code truly race free because t
VFIO TCE IOMMU v2 owns IOMMU tables so when detach a IOMMU group from
a container, we need to unset those from a group so we call unset_window()
so do we unconditionally. We also unset tables when removing a DMA window
via the VFIO_IOMMU_SPAPR_TCE_REMOVE ioctl.
The window removal checks if the tab
We store 2 multilevel tables in iommu_table - one for the hardware and
one with the corresponding userspace addresses. Before allocating
the tables, the iommu_table_group_ops::get_table_size() hook returns
the combined size of the two and VFIO SPAPR TCE IOMMU driver adjusts
the locked_vm counter co
On Sat, Feb 09, 2019 at 09:10:58PM +, Darren Stevens wrote:
> Hello Christoph
>
> On 08/02/2019, Christoph Hellwig wrote:
> > On Fri, Feb 08, 2019 at 10:01:46AM +0100, Christian Zigotzky wrote:
> >> Hi Christoph,
> >>
> >> Your new patch fixes the problems with the P.A. Semi Ethernet! :-)
> >
* Waiman Long wrote:
> On 02/07/2019 02:51 PM, Davidlohr Bueso wrote:
> > On Thu, 07 Feb 2019, Waiman Long wrote:
> >> 30 files changed, 1197 insertions(+), 1594 deletions(-)
> >
> > Performance numbers on numerous workloads, pretty please.
> >
> > I'll go and throw this at my mmap_sem intensiv
On Sun, Feb 10, 2019 at 01:00:20PM +0100, Christian Zigotzky wrote:
> I tested the whole series today. The kernels boot and the P.A. Semi
> Ethernet works! :-) Thanks a lot!
>
> I also tested it in a virtual e5500 QEMU machine today. Unfortunately the
> kernel crashes.
This looks like a patch I
Hi Christoph,
Mario successfully tested a kernel from your Git [1] on his T2080rdb today.
Link to the log:
https://gitlab.com/oshw-powerpc-notebook/T2080customizations/blob/master/kernel/dma_fix/kernel_dma_fix_log.txt
He wrote:
Please, note that all of the above kernel runs just fine with the
* Waiman Long wrote:
> On 02/10/2019 09:00 PM, Waiman Long wrote:
> > As the generic rwsem-xadd code is using the appropriate acquire and
> > release versions of the atomic operations, the arch specific rwsem.h
> > files will not be that much faster than the generic code as long as the
> > atom
On Mon, 2019-02-11 at 13:38 +1100, David Gibson wrote:
>
> 1) All in kernel
>
> The offset always maps directly to guest irq number and the kernel
> somehow binds it either to an IPI or a host irq as necessary.
> Cédric's original code attempts this, but the mechanism of keeping a
> pointer to th
Le 11/02/2019 à 01:21, Benjamin Herrenschmidt a écrit :
On Fri, 2019-02-08 at 12:52 +, Christophe Leroy wrote:
/*
+ * MSR_KERNEL is > 0x8000 on 4xx/Book-E since it include MSR_CE.
+ */
+.macro __LOAD_MSR_KERNEL r, x
+.if \x >= 0x8000
+ lis \r, (\x)@h
+ ori \r, \r, (\x)@l
+.e
On Sat, Feb 09, 2019 at 10:41:38AM +0100, Cédric Le Goater wrote:
> On 2/8/19 10:53 PM, Paul Mackerras wrote:
> > On Fri, Feb 08, 2019 at 08:58:14AM +0100, Cédric Le Goater wrote:
> >> On 2/8/19 6:15 AM, David Gibson wrote:
> >>> On Thu, Feb 07, 2019 at 10:03:15AM +0100, Cédric Le Goater wrote:
> >
Hi Vinod,
Got it.
Best Regards
Peng
>-Original Message-
>From: Vinod Koul
>Sent: 2019年2月4日 15:28
>To: Peng Ma
>Cc: Scott Wood ; Leo Li ; Zhang Wei
>; linuxppc-dev@lists.ozlabs.org;
>dmaeng...@vger.kernel.org; Wen He
>Subject: Re: [PATCH] dmaengine: fsldma: Add 64-bit I/O accessors for
Oliver writes:
> On Fri, Feb 8, 2019 at 11:32 PM Michael Ellerman wrote:
>> Oliver O'Halloran writes:
>>
>> > This patch adds a debugfs interface to force scheduling a recovery event.
>> > This can be used to recover a specific PE or schedule a "special" recovery
>> > even that checks for errors
Oliver writes:
> On Fri, Feb 8, 2019 at 8:47 PM Michael Ellerman wrote:
>> Oliver O'Halloran writes:
>> > diff --git a/arch/powerpc/kernel/eeh_cache.c
>> > b/arch/powerpc/kernel/eeh_cache.c
>> > index b2c320e0fcef..dba421a577e7 100644
>> > --- a/arch/powerpc/kernel/eeh_cache.c
>> > +++ b/arch/p
On 02/10/2019 09:00 PM, Waiman Long wrote:
> As the generic rwsem-xadd code is using the appropriate acquire and
> release versions of the atomic operations, the arch specific rwsem.h
> files will not be that much faster than the generic code as long as the
> atomic functions are properly implement
As the generic rwsem-xadd code is using the appropriate acquire and
release versions of the atomic operations, the arch specific rwsem.h
files will not be that much faster than the generic code as long as the
atomic functions are properly implemented. So we can remove those arch
specific rwsem.h an
On Fri, 2019-02-08 at 14:51 +, Mark Cave-Ayland wrote:
>
> Indeed, but there are still some questions to be asked here:
>
> 1) Why were these bits removed from the original bitmask in the first place
> without
> it being documented in the commit message?
>
> 2) Is this the right fix? I'm to
Hi Sandipan,
> This aims to add a test infrastructure for the in-kernel instruction
> emulation code. This is currently limited to testing only the basic
> integer operations and supports verification of the GPRs, LR, XER and
> CR.
>
> There can be multiple test cases for each instruction. Each te
Hi Sandipan,
> + {
> + .descr = "RA = LONG_MIN | INT_MIN, RB =
> LONG_MIN | INT_MIN",
> + .instr = PPC_INST_ADDC | ___PPC_RT(20) |
> ___PPC_RA(21) | ___PPC_RB(22),
> + .regs =
> +
Hi Sandipan,
I'm not really confident to review the asm, but I did have a couple of
questions about the C:
> +#define MAX_INSNS32
This doesn't seem to be used...
> +int execute_instr(struct pt_regs *regs, unsigned int instr)
> +{
> + extern unsigned int exec_instr_execute[];
> + exte
On Fri, 2019-02-08 at 12:52 +, Christophe Leroy wrote:
> /*
> + * MSR_KERNEL is > 0x8000 on 4xx/Book-E since it include MSR_CE.
> + */
> +.macro __LOAD_MSR_KERNEL r, x
> +.if \x >= 0x8000
> + lis \r, (\x)@h
> + ori \r, \r, (\x)@l
> +.else
> + li \r, (\x)
> +.endif
> +.endm
>
From: Michael Ellerman
In cpufeatures_process_feature(), if a provided CPU feature is unknown and
enable_unknown is false, we erroneously print that the feature is being
enabled and return true, even though no feature has been enabled, and
may also set feature bits based on the last entry in the
kcov provides kernel coverage data that's useful for fuzzing tools like
syzkaller.
Wire up kcov support on powerpc. Disable kcov instrumentation on the same
files where we currently disable gcov and UBSan instrumentation.
Signed-off-by: Andrew Donnellan
Acked-by: Dmitry Vyukov
---
arch/powerpc
Deepa Dinamani writes:
>> You touched powerpc in the previous patch but not this one.
>>
>> That's because we use the asm-generic version I assume.
>
> That is correct.
>
>> Would be good to mention in the change log though to avoid any confusion.
>
> I'm not sure how to do that now. It looks lik
Le 08/02/2019 à 13:52, Christophe Leroy a écrit :
This patch implements a fast entry for syscalls.
Syscalls don't have to preserve non volatile registers except LR.
This patch then implement a fast entry for syscalls, where
volatile registers get clobbered.
As this entry is dedicated to sys
Hello Aneesh,
On Fri, 8 Feb 2019 20:44:18 +0530
"Aneesh Kumar K.V" wrote:
> With this patch, we use the mtd->name instead of concatenating the name with
> '0'
>
> Fixes: c4dfa25ab307 ("mtd: add support for reading MTD devices via the nvmem
> API")
> Signed-off-by: Aneesh Kumar K.V
You forg
Hi Christoph,
On 08 February 2019 at 10:18AM, Christoph Hellwig wrote:
On Fri, Feb 08, 2019 at 10:01:46AM +0100, Christian Zigotzky wrote:
Hi Christoph,
Your new patch fixes the problems with the P.A. Semi Ethernet! :-)
Thanks a lot once again for testing!
Now can you test with this patch an
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