On Mon, 2018-06-18 at 12:13 +1000, Alexey Kardashevskiy wrote:
> On Sat, 16 Jun 2018 11:05:19 +1000
> Benjamin Herrenschmidt wrote:
>
> > On Fri, 2018-06-01 at 18:10 +1000, Alexey Kardashevskiy wrote:
> > > These are found in POWER9 chips. Right now these PHBs have unknown type
> > > so changing
Hi all,
On Tue, 12 Jun 2018 12:26:40 +1000 Stephen Rothwell
wrote:
>
> Building Linus' tree, today's linux-next build (powerpc allyesconfig)
> failed like this:
>
> ld: net/bpfilter/bpfilter_umh.o: compiled for a little endian system and
> target is big endian
> ld: failed to merge target spec
On 06/17/2018 01:22 PM, Venkat Rao B wrote:
On Friday 15 June 2018 07:14 PM, Michael Ellerman wrote:
vrbagal1 writes:
Hi,
Observing kernel bug followed by kernel oops and system reboots, while
running kselftest on Power8 LPAR.
Machine Details: Power8 LPAR
Git Tree:
https://git.kernel.org/
On Sat, 16 Jun 2018 11:05:19 +1000
Benjamin Herrenschmidt wrote:
> On Fri, 2018-06-01 at 18:10 +1000, Alexey Kardashevskiy wrote:
> > These are found in POWER9 chips. Right now these PHBs have unknown type
> > so changing it to PHB4 won't make much of a difference except enabling
> > sketchy bypa
On 06/17/2018 03:27 AM, Andreas Schwab wrote:
>
> That doesn't change anything.
OK, thanks !
Oh this is silly, please try :
diff --git a/net/core/skbuff.c b/net/core/skbuff.c
index
c642304f178ce0a4e1358d59e45032a39f76fb3f..54dd9c18ecad817812898d6f335e1794a07dabbe
100644
--- a/net/core/skb
The workaround has been removed. What stays is just code to find the
memory hole so the BATs can be configured properly in the function below.
Fixes: 57deb8fea01f ("powerpc/wii: Don't rely on the reserved memory hack")
Signed-off-by: Jonathan Neuschäfer
---
arch/powerpc/platforms/embedded6xx/wii
On Fri, 15 Jun 2018 21:37:15 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
> > On Wed, 13 Jun 2018 23:24:14 +1000
> > Michael Ellerman wrote:
> >
> >> When we take an SLB multi-hit on bare metal, we see both the multi-hit
> >> and parity error bits set in DSISR. The user manuals ind
This moves actual pages allocation to a separate function which is going
to be reused later in on-demand TCE allocation.
While we are at it, remove unnecessary level size round up as the caller
does this already.
Reviewed-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/pl
We are going to reuse multilevel TCE code for the userspace copy of
the TCE table and since it is big endian, let's make the copy big endian
too.
Reviewed-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/iommu.h| 2 +-
arch/powerpc/kvm/book3s_64_vio.c|
This gets rid of a useless wrapper around
pnv_pci_ioda2_table_free_pages().
Reviewed-by: David Gibson
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/pci-ioda.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-io
This patchset aims to reduce actual memory use for guests with
sparse memory. The pseries guest uses dynamic DMA windows to map
the entire guest RAM but it only actually maps onlined memory
which may be not be contiguous. I hit this when tried passing
through NVLink2-connected GPU RAM of NVIDIA V
At the moment we allocate the entire TCE table, twice (hardware part and
userspace translation cache). This normally works as we normally have
contigous memory and the guest will map entire RAM for 64bit DMA.
However if we have sparse RAM (one example is a memory device), then
we will allocate TCE
We want to support sparse memory and therefore huge chunks of DMA windows
do not need to be mapped. If a DMA window big enough to require 2 or more
indirect levels, and a DMA window is used to map all RAM (which is
a default case for 64bit window), we can actually save some memory by
not allocation
Right now we have allocation code in pci-ioda.c and traversing code in
pci.c, let's keep them toghether. However both files are big enough
already so let's move this business to a new file.
While we at it, move the code which links IOMMU table groups to
IOMMU tables as it is not specific to any PN
On Jun 16 2018, Eric Dumazet wrote:
> I would try something like :
>
> Basically do not bother using CHECKSUM_COMPLETE for small frames that might
> have been padded.
>
> Since we need to bring one cache line in eth_type_trans() and further header
> processing,
> computing the checksum in softw
On Jun 16 2018, Mathieu Malaterre wrote:
> That's odd since it seems to only affect g4+sungem user. None of the
> ppc64 seems to be having it.
I'm also seeing it on a PowerMac G5.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780
Use new return type vm_fault_t for fault handler. For
now, this is just documenting that the function returns
a VM_FAULT value rather than an errno. Once all instances
are converted, vm_fault_t will become a distinct type.
Ref-> commit 1c8f422059ae ("mm: change return type to vm_fault_t")
In this
On Friday 15 June 2018 07:14 PM, Michael Ellerman wrote:
vrbagal1 writes:
Hi,
Observing kernel bug followed by kernel oops and system reboots, while
running kselftest on Power8 LPAR.
Machine Details: Power8 LPAR
Git Tree:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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